Motor Controller (MC10B8CV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
680
Freescale Semiconductor
20.4.1.1.1
Dual Full H-Bridge Mode (MCOM = 11)
PWM channel pairs x and x + 1 operate in dual full H-bridge mode if both channels have been enabled
(MCAM[1:0]=01, 10, or 11) and both of the corresponding output mode bits MCOM[1:0] in both PWM
channel control registers are set.
A typical configuration in dual full H-bridge mode is shown in
Figure 20-10
. PWM channel x drives the
PWM output signal on either MnC0P or MnC0M. If MnC0P drives the PWM signal, MnC0M will be
output either high or low depending on the RECIRC bit. If MnC0M drives the PWM signal, MnC0P will
be an output high or low. PWM channel x + 1 drives the PWM output signal on either MnC1P or MnC1M.
If MnC1P drives the PWM signal, MnC1M will be an output high or low. If MnC1M drives the PWM
signal, MnC1P will be an output high or low. This results in motor recirculation currents on the high side
drivers (RECIRC = 0) while the PWM signal is at a logic high level, or motor recirculation currents on the
low side drivers (RECIRC = 1) while the PWM signal is at a logic low level. The pin driving the PWM
signal is determined by the S (sign) bit in the corresponding duty cycle register and the state of the
RECIRC bit. The value of the PWM duty cycle is determined by the value of the D[10:0] or D[8:2] bits
respectively in the duty cycle register depending on the state of the FAST bit.
1
MCMC2
MCDC2
PWM Channel 2
M1C0M
M1C0P
MCMC3
MCDC3
PWM Channel 3
M1C1M
M1C1P
2
MCMC4
MCDC4
PWM Channel 4
M2C0M
M2C0P
MCMC5
MCDC5
PWM Channel 5
M2C1M
M2C1P
3
MCMC6
MCDC6
PWM Channel 6
M3C0M
M3C0P
MCMC7
MCDC7
PWM Channel 7
M3C1M
M3C1P
Table 20-11. Corresponding Registers and Pin Names for Each PWM Channel Pair (continued)
PWM
Channel
Pair Number
PWM
Channel Control
Register
Duty Cycle
Register
Channel
Number
Pin
Names
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