Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.01
74
Freescale Semiconductor
2.3
Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
2.3.1
Memory Map
Table 2-2
shows the register map of the Port Integration Module.
1
Signals in brackets denote alternative module routing pins.
2
Function active when RESET asserted.
Table 2-2. Block Memory Map
Port
Offset or
Address
Register
Access
Reset Value
Section/Page
A
B
0x0000
PORTA—Port A Data Register
R/W
0x00
2.3.3/2-86
0x0001
PORTB—Port B Data Register
R/W
0x00
2.3.4/2-87
0x0002
DDRA—Port A Data Direction Register
R/W
0x00
2.3.5/2-87
0x0003
DDRB—Port B Data Direction Register
R/W
0x00
2.3.6/2-88
0x0004
:
:
0x0009
PIM Reserved
R
0x00
2.3.9/2-90
0x000A
:
0x000B
Non-PIM address range
1
-
-
-
A
B
0x000C
PUCR—Pull-up Up Control Register
R/W
2
0x43
2.3.8/2-89
0x000D
PIM Reserved
R/W
0x00
2.3.9/2-90
0x000E
:
0x001B
Non-PIM address range
1
-
-
-
0x001C
ECLKCTL—ECLK Control Register
R/W
0x80
2.3.10/2-91
0x001D
PIM Reserved
R
0x00
2.3.11/2-91
0x001E
IRQCR—IRQ Control Register
R/W
2
0x00
2.3.12/2-92
0x001F
PIM Reserved
R
0x00
2.3.13/2-92
0x0020
:
0x023F
Non-PIM address range
1
-
-
-
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