Electrical Characteristics
MC9S12XHY-Family Reference Manual, Rev. 1.01
Freescale Semiconductor
749
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in
Figure A-4
.
Figure A-4. Jitter Definitions
The relative deviation of t
nom
is at its maximum for one clock period, and decreases towards zero for larger
number of clock periods (N).
Defining the jitter as:
For N < 1000, the following equation is a good fit for the maximum jitter:
Figure A-5. Maximum bus clock jitter approximation
2
3
N-1
N
1
0
t
nom
t
max1
t
min1
t
maxN
t
minN
J N
( )
max 1
t
max
N
( )
N t
nom
⋅
-----------------------
–
1
t
min
N
( )
N t
nom
⋅
-----------------------
–
,
⎝
⎠
⎜
⎟
⎛
⎞
=
J N
( )
j
1
N
--------
j
2
+
=
1
5
10
20
N
J(N)
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