Electrical Characteristics
MC9S12XHY-Family Reference Manual, Rev. 1.01
754
Freescale Semiconductor
A.9
SPI Timing
This section provides electrical parametrics and ratings for the SPI. In
Table A-25
the measurement
conditions are listed.
A.9.1
Master Mode
In
Figure A-9
the timing diagram for master mode with transmission format CPHA = 0 is depicted.
Figure A-9. SPI Master Timing (CPHA = 0)
Table A-25. Measurement Conditions
Description
Value
Unit
Drive mode
Full drive mode
—
Load capacitance C
LOAD
1
,
on all outputs
1
Timing specified for equal load on all SPI output pins. Avoid asymmetric load.
50
pF
Thresholds for delay measurement points
(20% / 80%) V
DDX
V
Thresholds for delay measurement points on Motor pad
(20% / 80%) V
DDM
V
SCK
(Output)
SCK
(Output)
MISO
(Input)
MOSI
(Output)
SS
(Output)
1
9
5
6
MSB IN2
Bit MSB-1. . . 1
LSB IN
MSB OUT2
LSB OUT
Bit MSB-1. . . 1
11
4
4
2
10
(CPOL = 0)
(CPOL = 1)
3
13
13
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.
12
12
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