Chapter 4 Interrupt (S12ZINTV0)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
132
Freescale Semiconductor
4.3.2.1
Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
4.3.2.2
Interrupt Request Configuration Address Register (INT_CFADDR)
Read: Anytime
0x00001D INT_CFDATA5 R
0
0
0
0
0
PRIOLVL[2:0]
W
0x00001E INT_CFDATA6 R
0
0
0
0
0
PRIOLVL[2:0]
W
0x00001F INT_CFDATA7 R
0
0
0
0
0
PRIOLVL[2:0]
W
Address: 0x000010
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
IVB_ADDR[15:1]
0
W
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Figure 4-3. Interrupt Vector Base Register (IVBR)
Table 4-4. IVBR Field Descriptions
Field
Description
15–1
IVB_ADDR
[15:1]
Interrupt Vector Base Address Bits
— These bits represent the upper 15 bits of all vector addresses. Out
of reset these bits are set to 0xFFFE (i.e., vectors are located at 0xFFFE00–0xFFFFFF).
Note:
A system reset will initialize the interrupt vector base register with “0xFFFE” before it is used to
determine the reset vector address. Therefore, changing the IVBR has no effect on the location of the
reset vector (0xFFFFFC–0xFFFFFF).
Address: 0x000017
7
6
5
4
3
2
1
0
R
0
INT_CFADDR[6:3]
0
0
0
W
Reset
0
0
0
0
1
0
0
0
= Unimplemented or Reserved
Figure 4-4. Interrupt Configuration Address Register (INT_CFADDR)
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 4-2. INT Register Summary
