Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
282
Freescale
Semiconductor
7.4.3
Stop Mode using PLLCLK as source of the Bus Clock
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in
. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode.
Figure 7-37. Stop Mode using PLLCLK as source of the Bus Clock
Depending on the COP configuration there might be an additional significant latency time until COP is
active again after exit from Stop Mode due to clock domain crossing synchronization. This latency time
occurs if COP clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for
details).
7.4.4
Full Stop Mode using Oscillator Clock as source of the Bus Clock
An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is
shown in
.
Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going
into Full Stop Mode.
PLLCLK
CPU
LOCK
t
lock
STOP instruction
execution
interrupt
continue execution
wake up
t
STP_REC
