Chapter 7 S12 Clock, Reset and Power Management Unit (S12CPMU_UHV_V5)
S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
288
Freescale
Semiconductor
7.5.4
PLL Clock Monitor Reset
In case of loss of PLL clock oscillation or the PLL clock frequency is below the failure assert frequency
f
PMFA
(see device electrical characteristics for values), the S12CPMU_UHV_V5 generates a PLL Clock
Monitor Reset. In Full Stop Mode the PLL and the PLL clock monitor are disabled.
7.5.5
Computer Operating Properly Watchdog (COP) Reset
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus COP reset is generated.
The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL0 and COPOSCSEL1 bit.
Depending on the COP configuration there might be a significant latency time until COP is active again
after exit from Stop Mode due to clock domain crossing synchronization. This latency time occurs if COP
clock source is ACLK and the CSAD bit is set (please refer to CSAD bit description for details)
gives an overview of the COP condition (run, static) in Stop Mode depending on legal
configuration and status bit settings:
Table 7-35. COP condition (run, static) in Stop Mode
COPOSCSEL1 CSAD PSTP
PCE
COPOSCSEL0
OSCE
UPOSC
COP counter behavior in Stop Mode
(clock source)
1
0
x
x
x
x
x
Run (ACLK)
1
1
x
x
x
x
x
Static (ACLK)
0
x
1
1
1
1
1
Run (OSCCLK)
0
x
1
1
0
0
x
Static (IRCCLK)
0
x
1
1
0
1
x
Static (IRCCLK)
0
x
1
0
0
x
x
Static (IRCCLK)
0
x
1
0
1
1
1
Static (OSCCLK)
0
x
0
1
1
1
1
Static (OSCCLK)
0
x
0
1
0
1
x
Static (IRCCLK)
0
x
0
1
0
0
0
Static (IRCCLK)
0
x
0
0
1
1
1
Satic (OSCCLK)
0
x
0
0
0
1
1
Static (IRCCLK)
0
x
0
0
0
1
0
Static (IRCCLK)
0
x
0
0
0
0
0
Static (IRCCLK)
