Chapter 1 Device Overview MC9S12ZVHY/MC9S12ZVHL Families
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
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1.7.2.25.2
BP[3:0] Signals
These signals are associate the segment LCD backplane driver output.
1.7.2.26
RTC Signals
1.7.2.26.1
RTC_CAL Signal
The signal can be the RTC output clock CALCLK for external clock calibration or external 1HZ standard
clock input for on chip clock calibration.
1.7.2.27
SSG0 Signals
1.7.2.27.1
SGT0 Signals
The signal is from SSG0 output, it contain tone or tone mixed with amplitude digital output.
1.7.2.27.2
SGA0 Signals
The signal is from SSG0 output, it contain the amplitude digital output.
1.7.2.28
IIC0 Signals
1.7.2.28.1
SDA0 Signal
This signal is associated with the serial data pin of IIC0.
1.7.2.28.2
SCL0 Signal
This signal is associated with the serial clock pin of IIC0.
1.7.2.29
MC Signals
1.7.2.29.1
M0C0M, M0C0P, M0C1M and M0C1P Signals
These signal are associated with the high current PWM out pin for the motor driver.
1.7.2.29.2
M1C0M, M1C0P, M1C1M and M1C1P Signals
These signal are associated with the high current PWM out pin for the motor driver.
1.7.2.30
SSD[1:0] Signals
1.7.2.30.1
M0COSM, M0COSP, M0SINM and M0SINP Signals
These signal are used to measure the back EMF to calibrate the pointer reset position which are associated
with SSD[0].
