Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
447
shows the common 13-byte data structure of receive and transmit buffers for extended
identifiers. The mapping of standard identifiers into the IDR registers is shown in
.
All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation
1
.
All reserved or unused bits of the receive and transmit buffers always read ‘x’.
Table 11-25. Message Buffer Organization
Offset
Address
Register
Access
0x00X0
IDR0 — Identifier Register 0
R/W
0x00X1
IDR1 — Identifier Register 1
R/W
0x00X2
IDR2 — Identifier Register 2
R/W
0x00X3
IDR3 — Identifier Register 3
R/W
0x00X4
DSR0 — Data Segment Register 0
R/W
0x00X5
DSR1 — Data Segment Register 1
R/W
0x00X6
DSR2 — Data Segment Register 2
R/W
0x00X7
DSR3 — Data Segment Register 3
R/W
0x00X8
DSR4 — Data Segment Register 4
R/W
0x00X9
DSR5 — Data Segment Register 5
R/W
0x00XA
DSR6 — Data Segment Register 6
R/W
0x00XB
DSR7 — Data Segment Register 7
R/W
0x00XC
DLR — Data Length Register
R/W
0x00XD
TBPR — Transmit Buffer Priority Register
(1)
1. Not applicable for receive buffers
R/W
0x00XE
TSRH — Time Stamp Register (High Byte)
R
0x00XF
TSRL — Time Stamp Register (Low Byte)
R
1. Exception: The transmit buffer priority registers are 0 out of reset.
