Chapter 12 Serial Communication Interface (S12SCIV6)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
490
Freescale Semiconductor
12.3.2.9
SCI Data Registers (SCIDRH, SCIDRL)
Read: Anytime; reading accesses SCI receive data register
Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect
NOTE
The reserved bit SCIDRH[2:0] are designed for factory test purposes only,
and are not intended for general user access. Writing to these bit is possible
when in special mode and can alter the modules functionality.
NOTE
If the value of T8 is the same as in the previous transmission, T8 does not
have to be rewritten.The same value is transmitted until T8 is rewritten
In 8-bit data format, only SCI data register low (SCIDRL) needs to be
accessed.
Module Base + 0x0006
7
6
5
4
3
2
1
0
R
R8
T8
0
0
0
Reserved
Reserved
Reserved
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-12. SCI Data Registers (SCIDRH)
Module Base + 0x0007
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
Reset
0
0
0
0
0
0
0
0
Figure 12-13. SCI Data Registers (SCIDRL)
Table 12-13. SCIDRH and SCIDRL Field Descriptions
Field
Description
SCIDRH
7
R8
Received Bit 8
— R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
SCIDRH
6
T8
Transmit Bit 8
— T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
SCIDRL
7:0
R[7:0]
T[7:0]
R7:R0
— Received bits seven through zero for 9-bit or 8-bit data formats
T7:T0
— Transmit bits seven through zero for 9-bit or 8-bit formats
