Chapter 18 Real-Time Counter With Calendar (RTCV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
644
Freescale Semiconductor
18.4.2 RTC Control Register 2 (RTCCTL2)
The RTCCTL2 contains the RTC clock source selection bit and clock divider control bits. This register is
write one time only in normal mode, anytime in special mode.
18.4.3 RTC Control Register 3 (RTCCTL3)
The RTCCTL3 contains the write protection configure bits (RTCWE1, RTCW0), the compensation data
setting ready bit.
7
6
5
4
3
2
1
0
R
CLKSRC1
CLKSRC0
0
0
RTCPS3
RTCPS2
RTCPS1
RTCPS0
W
POR:
0
0
0
0
0
0
0
0
Figure 18-3. RTC Control Register 2(RTCCTL2)
Table 18-4. RTCCTL2 Field Descriptions
Field
Description
7:6
CLKSRC
RTC Clock Source Selection
— The read/write bit select the RTCCLK source.
00 RTCCLK is from OSCCLK
01 RTCCLK is from OSCCLK_32K
10 RTCCLK is from IRCCLK
11 reserved
3:0
RTCPS
RTC main OSC prescaler
— These read/write bits define the OSCCLK prescaler value. The input OSCCLK
will be divided by (RTCPS+1) if RTCLK source is from OSCCLK. User should set the RTCPS value to let
prescaler clock frequency to be 1MHZ. The 1MHZ clock will be divide by 32 to generate 31.25KHz RTC counter
clock.
7
6
5
4
3
2
1
0
R
0
0
FRZ
0
CALS
0
W
RTCWE1
RTCWE0
Reset:
0
0
0
0
0
0
0
0
Figure 18-4. RTC Control Register 3(RTCCTL3)
