Chapter 21 64 KB Flash Module (S12ZFTMRZ64K2KV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
704
Freescale Semiconductor
21.3.2.7
Flash Status Register (FSTAT)
The FSTAT register reports the operational status of the Flash module.
CCIF, ACCERR, and FPVIOL bits are readable and writable, MGBUSY and MGSTAT bits are readable
but not writable, while remaining bits read 0 and are not writable.
Table 21-16. FERCNFG Field Descriptions
Field
Description
0
SFDIE
Single Bit Fault Detect Interrupt Enable
— The SFDIE bit controls interrupt generation when a single bit fault
is detected during a Flash block read operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set (see
)
1 An interrupt will be requested whenever the SFDIF flag is set (see
Offset Module Base + 0x0006
7
6
5
4
3
2
1
0
R
CCIF
0
ACCERR
FPVIOL
MGBUSY
RSVD
MGSTAT[1:0]
W
Reset
1
0
0
0
0
0
0
(1)
1. Reset value can deviate from the value shown if a double bit fault is detected during the reset sequence (see
).
= Unimplemented or Reserved
Figure 21-11. Flash Status Register (FSTAT)
Table 21-17. FSTAT Field Descriptions
Field
Description
7
CCIF
Command Complete Interrupt Flag
— The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
5
ACCERR
Flash Access Error Flag
— The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see
) or issuing an illegal Flash
command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is
cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
4
FPVIOL
Flash Protection Violation Flag
—The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash or EEPROM memory during a command write sequence. The FPVIOL
bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL
is set, it is not possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
3
MGBUSY
Memory Controller Busy Flag
— The MGBUSY flag reflects the active state of the Memory Controller
.
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
