Appendix C PLL Electrical Specifications
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
796
Freescale Semiconductor
Figure C-2. Maximum Bus Clock Jitter Approximation (N = number of Bus Cycles)
NOTE
On timers and serial modules a prescaler will eliminate the effect of the jitter
to a large extent.
Table C-1. ipll_1vdd_ll18 Characteristics
Conditions are 4.5 V < V
DDX
< 5.5 V junction temperature from –40
C to +150
C, unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
D
VCO frequency during system reset
f
VCORST
8
32
MHz
2
C
VCO locking range
f
VCO
32
64
MHz
3
C
Reference Clock
f
REF
1
MHz
4
D
Lock Detection Threshold
Lock
|
0
1.5
%
(1)
1. % deviation from target frequency
5
D
Un-Lock Detection Threshold
unl
|
0.5
2.5
%
1
7
C
Time to lock
t
lock
150 +
256/f
REF
s
8
C
Jitter fit parameter 1
(2)
2. f
REF
= 1MHz, f
BUS
= 32MHz
j
1
2
%
9
P PLL Clock Monitor Failure assert frequency
f
PMFA
0.45
1.1
1.6
MHz
J N
j
1
N POSTDIV 1
+
--------------------------------------------------
=
1
5
10
20
N
J(N)
