Chapter 2 Port Integration Module (S12ZVHYPIMV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
95
NOTE
For standalone usage of SCI0 on external pins set
[S0L0RR2:S0L0RR0]=0b110 and disable the LINPHY0 (LPCR[LPE]=0).
This releases PC3 and PC2 to other associated functions and maintains
TXD0 and RXD0 signals on PS7 and PS6, respectively, if no other function
with higher priority takes precedence.
2.3.2.5
ECLK Control Register (ECLKCTL)
2.3.2.6
IRQ Control Register (IRQCR)
Address 0x0208
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
NECLK
0
0
0
0
0
0
0
W
Reset:
1
0
0
0
0
0
0
0
Figure 2-6. ECLK Control Register (ECLKCTL)
Table 2-6. ECLKCTL Register Field Descriptions
Field
Description
7
NECLK
No ECLK
— Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
Address 0x0209
Access: User read/write
(1)
1. Read: Anytime
Write:
IRQE: Once in normal mode, anytime in special mode
IRQEN:
Anytime
7
6
5
4
3
2
1
0
R
IRQE
IRQEN
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-7. IRQ Control Register (IRQCR)
