S12ZVHY/S12ZVHL Family Reference Manual, Rev. 1.05
Freescale Semiconductor
229
Chapter 7
S12 Clock, Reset and Power Management Unit
(S12CPMU_UHV_V5)
Table 7-1.
Revision History
7.1
Introduction
This specification describes the function of the Clock, Reset and Power Management Unit
(S12CPMU_UHV_V5).
•
The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock
source. It is designed for optimal start-up margin with typical crystal oscillators.
•
The Voltage regulator (VREGAUTO) operates from the range 6V to 18V. It provides all the
required chip internal voltages and voltage monitors.
•
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
•
The Internal Reference Clock (IRC1M) provides a 1MHz internal clock.
Rev. No.
(Item No)
Date
(Submitted By)
Sections Affected
Substantial Change(s)
V05.11
21 Aug.2013
• changed frequency upper limit of external Pierce Oscillator
(XOSCLCP) from 16MHz to 20MHz
• f
PLLRST
changed to f
VCORST
• correct bit numbering for CSAD Bit
• corrected typo in heading of CPMUOSC
2
Field Description
V05.12
20 Feb.2014
• corrected description of CSAD bit
• Refined description of STOP mode entry. Added reference to
device specification because BDC running in Stop mode does
not lead to CPMU going in Stop Mode.
V05.13
21 Oct. 2014
• Improved Figure: Start up of clock system after Reset
• Improved Figure: Full stop mode using Oscillator
• Improved Figure: Enabling the external oscillator
• Improved Table: Trimming effect of ACLKTR
• Improved Table: Trimming effect of HTTR
• Register Description for CPMUHTCTL: Added note on how to
compute V
HT
• Functional Description PBE Mode: Added Note that the clock
system might stall if osc monitor reset disabled (OMRE=0)
• Signal Descriptions: changed recommended resistor for BCTL
pin to 1
K
