Chapter 1 Device Overview MC9S12ZVHY/MC9S12ZVHL Families
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
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Instructions and Addressing modes optimized for C-Programming & Compiler
— MAC unit 32bit += 32bit*32bit
— Hardware divider
— Single cycle multi-bit shifts (Barrel shifter)
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Special instructions for fixed point match
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Unimplemented opcode traps
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Unprogrammed byte value (0xFF) defaults to SWI instruction
1.5.1.1
Background Debug Controller (BDC)
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Background Debug Controller (BDC) with single-wire interface
— Non-intrusive memory access commands
— Supports in-circuit programming of on-chip nonvolatile memory
1.5.1.2
Debugger (DBG)
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Enhanced DBG module including:
— Four comparators (A, B, C and D) each configurable to monitor PC addresses or addresses of
data accesses
— A and C compare full address bus and full 32-bit data bus with data bus mask register
— B and D compare full address bus only
— Three modes: simple address/data match, inside address range, or outside address range
— Tag-type or force-type hardware breakpoint requests
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State sequencer control
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64 x 64-bit circular trace buffer to capture change-of-flow addresses or address and data of every
access
— Begin, End and Mid alignment of tracing to trigger
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Profiling mode
1.5.2
Embedded Memory
1.5.2.1
Flash
On-chip flash memory:
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Up to 64 KB of program flash memory
— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit fault correction
and double fault detection
— Erase sector size 512 bytes
— Automated program and erase algorithm
— User margin level setting for reads
— Protection scheme to prevent accidental program or erase
