Chapter 9 Pulse-Width Modulator (S12PWM8B8CV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
328
Freescale Semiconductor
9.3.2.1
PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due
to the synchronization of PWMEx and the clock source.
NOTE
The first PWM cycle after enabling the channel can be irregular.
An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their
corresponding PWM output lines are disabled.
While in run mode, if all existing PWM channels are disabled (PWMEx–0 = 0), the prescaler counter shuts
off for power savings.
Read: Anytime
Write: Anytime
0x0023
R
Bit 7
6
5
4
3
2
1
Bit 0
W
0x0024
RESERVED
R
0
0
0
0
0
0
0
0
W
0x0025
RESERVED
R
0
0
0
0
0
0
0
0
W
0x0026
RESERVED
R
0
0
0
0
0
0
0
0
W
0x0027
RESERVED
R
0
0
0
0
0
0
0
0
W
1. The related bit is available only if corresponding channel exists.
2. The register is available only if corresponding channel exists.
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
PWME7
PWME6
PWME5
PWME4
PWME3
PWME2
PWME1
PWME0
W
Reset
0
0
0
0
0
0
0
0
Figure 9-3. PWM Enable Register (PWME)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 9-2. The scalable PWM Register Summary (Sheet 4 of 4)
