Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
417
mode “Trigger Mode” only a Restart Event is necessary if ADC is idle to restart Conversion Sequence List
execution (the Trigger Event occurs automatically).
It is possible to set bit RSTA and SEQA simultaneously, causing a Sequence Abort Event followed by a
Restart Event. In this case the error flags behave differently depending on the selected conversion flow
control mode:
•
Setting both flow control bits simultaneously in conversion flow control mode “Restart Mode”
prevents the error flags RSTA_EIF and LDOK_EIF from occurring.
•
Setting both flow control bits simultaneously in conversion flow control mode “Trigger Mode”
prevents the error flag RSTA_EIF from occurring.
If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort
Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set.
Please see also the detailed conversion flow control bit mandatory requirements and execution information
for bit RSTA and SEQA described in
Section 10.5.3.2.5, “The four ADC conversion flow control bits
.
10.8.7.3
Restart CSL execution with new/other CSL (alternative CSL becomes
active CSL) — CSL swapping
After all alternative conversion command list entries are finished the bit LDOK can be set simultaneously
with the next Restart Event to swap command buffers.
To start conversion command list execution it is mandatory that the ADC is idle (no conversion or
conversion sequence is ongoing).
If necessary, a possible ongoing conversion sequence can be aborted by the Sequence Abort Event (setting
bit SEQA). As soon as bit SEQA is cleared by the ADC, the current conversion sequence has been aborted
and the ADC is idle (no conversion sequence or conversion ongoing).
After a conversion sequence abort is executed it is mandatory to request a Restart Event (bit RSTA set)
and simultaneously set bit LDOK to swap the CSL buffer. After the Restart Event is finished (bit RSTA
and LDOK are cleared), the ADC accepts a new Trigger Event (bit TRIG can be set) and begins conversion
from the top of the newly selected CSL buffer. In conversion flow control mode “Trigger Mode” only a
Restart Event (simultaneously with bit LDOK being set) is necessary to restart conversion command list
execution with the newly selected CSL buffer (the Trigger Event occurs automatically).
It is possible to set bits RSTA, LDOK and SEQA simultaneously, causing a Sequence Abort Event
followed by a Restart Event. In this case the error flags behave differently depending on the selected
conversion flow control mode:
•
Setting these three flow control bits simultaneously in “Restart Mode” prevents the error flags
RSTA_EIF and LDOK_EIF from occurring.
•
Setting these three flow control bits simultaneously in “Trigger Mode” prevents the error flag
RSTA_EIF from occurring.
If only a Restart Event occurs while ADC is not idle and bit SEQA is not set already (Sequence Abort
Event in progress) a Sequence Abort Event is issued automatically and bit RSTAR_EIF is set.
