Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
449
Read:
•
For transmit buffers, anytime when TXEx flag is set (see
Section 11.3.2.7, “MSCAN Transmitter
”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)
•
For receive buffers, only when RXF flag is set (see
Section 11.3.2.5, “MSCAN Receiver Flag
”).
Write:
•
For transmit buffers, anytime when TXEx flag is set (see
Section 11.3.2.7, “MSCAN Transmitter
”) and the corresponding transmit buffer is selected in CANTBSEL (see
Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)
•
Unimplemented for receive buffers.
Reset: Undefined because of RAM-based implementation
11.3.3.1
Identifier Registers (IDR0–IDR3)
The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE,
and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0],
RTR, and IDE.
= Unused, always read ‘x’
Figure 11-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
IDR0
0x00X0
R
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
W
IDR1
0x00X1
R
ID2
ID1
ID0
RTR
IDE (=0)
W
IDR2
0x00X2
R
W
IDR3
0x00X3
R
W
= Unused, always read ‘x’
Figure 11-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued)
Register
Name
Bit 7
6
5
4
3
2
1
Bit0
