Chapter 16 Motor Controller (MC10B8CV1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
609
Center aligned (MCAM[1:0] = 11): Even periods will be output left aligned, odd periods will be output
right aligned. PWM operation starts with the even period after the channel has been enabled. PWM
operation in center aligned mode might start with the odd period if the channel has not been disabled before
changing the alignment mode to center aligned.
16.4.1.3.2
Sign Bit (S)
Assuming RECIRC = 0 (the active state of the PWM signal is low), when the S bit for the corresponding
channel is cleared, MnC0P (if the PWM channel number is even, n = 0, 1, 2, 3, see
(if the PWM channel number is odd, n = 0, 1, 2, 3, see
), outputs a logic high while in (dual)
full H-bridge mode. In half H-bridge mode the state of the S bit has no effect. The PWM output signal is
generated on MnC0M (if the PWM channel number is even, n = 0, 1, 2, 3, see
) or MnC1M (if
the PWM channel number is odd, n = 0, 1, 2, 3).
Assuming RECIRC = 0 (the active state of the PWM signal is low), when the S bit for the corresponding
channel is set, MnC0M (if the PWM channel number is even, n = 0, 1, 2, 3, see
(if the PWM channel number is odd, n = 0, 1, 2, 3, see
), outputs a logic high while in (dual)
full H-bridge mode. In half H-bridge mode the state of the S bit has no effect. The PWM output signal is
generated on MnC0P (if the PWM channel number is even, n = 0, 1, 2, 3, see
) or MnC1P (if
the PWM channel number is odd, n = 0, 1, 2, 3).
0
85
PWM Output
0
1 Period
100 Counts
Motor Controller
Timer Counter
Motor Controller
Timer Counter
Clock
0
1 Period
100 Counts
85
99
99
DITH = 0, MCAM[1:0] = 10, MCDCx = 15, MCPER = 100, RECIRC = 0
0
85
PWM Output
0
1 Period
100 Counts
Motor Controller
Timer Counter
Motor Controller
Timer Counter
Clock
0
1 Period
100 Counts
15
99
99
DITH = 0, MCAM[1:0] = 11, MCDCx = 15, MCPER = 100, RECIRC = 0
