Chapter 21 64 KB Flash Module (S12ZFTMRZ64K2KV2)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
699
21.3.2.2
Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0xFF_FE0F located in P-Flash memory (see
) as
indicated by reset condition F in
. If a double bit fault is detected while reading the P-Flash
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set
to leave the Flash module in a secured state with backdoor key access disabled.
18.6
19.6
0x12
44.6
45.6
0x2C
19.6
20.6
0x13
45.6
46.6
0x2D
20.6
21.6
0x14
46.6
47.6
0x2E
21.6
22.6
0x15
47.6
48.6
0x2F
22.6
23.6
0x16
48.6
49.6
0x30
23.6
24.6
0x17
49.6
50.6
0x31
24.6
25.6
0x18
25.6
26.6
0x19
1. BUSCLK is Greater Than this value.
2. BUSCLK is Less Than or Equal to this value.
Offset Module Base + 0x0001
7
6
5
4
3
2
1
0
R
KEYEN[1:0]
RNV[5:2]
SEC[1:0]
W
Reset
F
(1)
1. Loaded from Flash configuration field, during reset sequence.
F
1
F
1
F
1
F
1
F
1
F
1
F
1
= Unimplemented or Reserved
Figure 21-6. Flash Security Register (FSEC)
Table 21-9. FSEC Field Descriptions
Field
Description
7–6
KEYEN[1:0]
Backdoor Key Security Enable Bits
— The KEYEN[1:0] bits define the enabling of backdoor key access to the
Flash module as shown in
Table 21-8. FDIV values for various BUSCLK Frequencies
BUSCLK Frequency
(MHz)
FDIV[5:0]
BUSCLK Frequency
(MHz)
FDIV[5:0]
MIN
(1)
MAX
(2)
MIN
1
MAX
2
