Power Management
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
8-6
Freescale Semiconductor
Preliminary
2. At the appropriate time, the processor executes the privileged STOP instruction. After the
processor has stopped execution, it asserts a specific Processor Status (PST) encoding. Issuing the
STOP instruction when the LPICR[ENBSTOP] bit is set causes the SCM to enter stop mode.
3. The entry into a low-power mode is processed by the low-power mode control logic, and the
appropriate clocks (usually those related to the high-speed processor core) are disabled.
4. After entering the low-power mode, the interrupt controller enables a combinational logic path
which evaluates any unmasked interrupt requests. The device waits for an event to generate an
interrupt request with a priority level greater than the value programmed in
LPICR[XLPM_IPL[2:0]].
NOTE
Only a fixed (external) interrupt can bring a device out of stop mode. To exit
from other low-power modes, such as doze or wait, fixed or programmable
interrupts may be used; however, the module generating the interrupt must
be enabled in that particular low-power mode.
5. After an appropriately high interrupt request level arrives, the interrupt controller signals its
presence, and the SCM responds by asserting the request to exit low-power mode.
6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.
7. With the processor clocks enabled, the core processes the pending interrupt request.
IPSBAR
Offset: 0x0012 (LPICR)
Access: read/write
7
6
5
4
3
2
1
0
R
ENBSTOP
XLPM_IPL[2:0]
0
0
0
0
W
Reset:
0
0
0
0
0
0
0
0
Figure 8-3. Low-Power Interrupt Control Register (LPICR)
Table 8-4. LPICR Field Description
Field
Description
7
ENBSTOP
Enable low-power stop mode.
0 Low-power stop mode disabled
1 Low-power stop mode enabled. After the core is stopped and the signal to enter stop mode is asserted,
processor clocks can be disabled.
6–4
XLPM_IPL
[2:0]
Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the
low-power mode.Refer to
3–0
—
Reserved, should be cleared.
