Power Management
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
8-8
Freescale Semiconductor
Preliminary
PPMR
x
to be zeroed, enabling all IPS module clocks. In the event on simultaneous writes of the PPMRS
and PPMRC, the write to the PPMRC takes priority. Reads of this register return all zeroes. See
and
8.2.5
Low-Power Control Register (LPCR)
The LPCR controls chip operation and module operation during low-power modes. It specifies the
low-power mode entered when the STOP instruction is issued, and controls clock activity in this
low-power mode.
IPSBAR
Offset: 0x0022 (PPMRC)
Access: write-only
7
6
5
4
3
2
1
0
R
0
W
PPMRC
Reset:
0
0
0
0
0
0
0
0
Figure 8-5. Peripheral Power Management Clear Register (PPMRC)
Table 8-7. PPMRC Field Descriptions
Field
Description
7
Reserved, should be cleared.
6–0
PPMRC
Clear Module Clock Disable
0–63 Clear corresponding bit in PPMR
x
, enabling the module clock
64–127 Clear all bits in PPMR
x
, enabling all the module clocks
IPSBAR
Offset: 0x11_0007 (LPCR)
Access: read/write
7
6
5
4
3
2
1
0
R
LPMD
0
STPMD
0
LVDSE
0
W
Reset:
0
0
0
0
0
0
1
0
Figure 8-6. Low-Power Control Register (LPCR)
