Power Management
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
8-14
Freescale Semiconductor
Preliminary
8.4.2.10
I/O Ports
The I/O ports are unaffected by entry into a low-power mode. These pins may impact low-power current
draw if they are configured as outputs and are sourcing current to an external load. If low-power mode is
exited by a reset, the state of the I/O pins reverts to their default direction settings.
8.4.2.11
Reset Controller
A power-on reset (POR) always causes a chip reset and exit from any low-power mode.
In wait and doze modes, asserting the external RESET pin for at least four clocks causes an external reset
that resets the chip and exit any low-power modes.
In stop mode, the RESET pin synchronization is disabled and asserting the external RESET pin
asynchronously generates an internal reset and exit any low-power modes. Registers lose current values
and must be reconfigured from reset state if needed.
If the phase lock loop (PLL) in the clock module is active and if the appropriate (LOCRE, LOLRE) bits
in the synthesizer control register are set, then any loss-of-clock or loss-of-lock resets the chip and exit any
low-power modes.
If the watchdog timer is enabled during wait or doze modes, then a watchdog timer timeout may generate
a reset to exit these low-power modes.
When the CPU is inactive, a software reset cannot be generated to exit any low-power mode.
8.4.2.12
Chip Configuration Module
The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode is
exited by a reset, chip configuration may be executed if configured to do so.
8.4.2.13
Clock Module
In wait and doze modes, the clocks to the CPU, flash, and SRAM are stopped and the system clocks to the
peripherals are enabled. Each module may disable the module clocks locally at the module level. In stop
mode, all clocks to the system are stopped.
During stop mode, the PLL continues to run. The external CLKOUT signal may be enabled or disabled
when the device enters stop mode, depending on the LPCR[STPMD] bit settings.The external CLKOUT
output pin may be disabled to lower power consumption via the SYNCR[DISCLK] bit. The external
CLKOUT pin function is enabled by default at reset.
8.4.2.14
Edge Port
In wait and doze modes, the edge port continues to operate normally and may be configured to generate
interrupts (an edge transition or low level on an external pin) to exit the low-power modes.
In stop mode, there is no system clock available to perform the edge detect function. Thus, only the level
detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an
interrupt (if enabled) to exit the stop mode.
