Chip Configuration Module (CCM)
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
9-2
Freescale Semiconductor
Preliminary
9.2.1
RCON
The serial flash programming mode is entered by asserting the RCON pin (with the TEST pin negated) as
the chip comes out of reset. While the device is in this mode, the EzPort has access to the flash memory,
which allows it to be programmed from an external device.
9.2.2
CLKMOD[1:0]
The state of the CLKMOD[1:0] pins during reset determines the clock mode after reset. Refer to
for more information.
9.2.3
JTAG_EN
The JTAG_EN signal is used to select between debug module (JTAG_EN = 0) and JTAG (JTAG_EN = 1)
modes at reset.
9.2.4
TEST
Reserved for factory testing only. In normal modes of operation, this pin must be connected to VSS to
avoid unintentional activation of test functions.
9.3
Memory Map/Register Definition
This subsection provides a description of the memory map and registers.
9.3.1
Programming Model
The CCM programming model consists of these registers:
•
The chip configuration register (CCR) controls the main chip configuration.
•
The reset configuration register (RCON) indicates the default chip configuration.
•
The chip identification register (CIR) contains a unique part number.
Table 9-2. Write-Once Bits Read/Write Accessibility
Configuration
Read/Write Access
All configurations
Read-always
Debug operation
Write-always
