DMA Controller Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
16-14
Freescale Semiconductor
Preliminary
As soon as the channel has been initialized, it is started by writing a one to DCR
n
[START] or a peripheral
DMA request, depending on the status of DCR
n
[EEXT]. Programming the channel for internal requests
causes the channel to request the bus and start transferring data immediately. If the channel is programmed
for external request, a peripheral DMA request must be asserted before the channel requests the bus.
Changes to DCR
n
are effective immediately while the channel is active. To avoid problems with changing
a DMA channel setup, write a one to DSR
n
[DONE] to stop the DMA channel.
16.4.4
Data Transfer
This section describes auto-alignment and bandwidth control for DMA transfers.
16.4.4.1
Auto-Alignment
Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and
programmed size. To use this feature, DCR
n
[AA] must be set. The source is auto-aligned if DCR
n
[SSIZE]
indicates a transfer size larger than DCR
n
[DSIZE]. Source alignment takes precedence over the
destination when the source and destination sizes are equal. Otherwise, the destination is auto-aligned. The
address register chosen for alignment increments regardless of the increment value. Configuration error
checking is performed on registers not chosen for alignment.
If BCR
n
is greater than 16, the address determines transfer size. Bytes, words, or longwords are transferred
until the address is aligned to the programmed size boundary, at which time accesses begin using the
programmed size.
If BCR
n
is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer size. For
example, AA equals 1, SAR
n
equals 0x0001, BCR
n
equals 0x00F0, SSIZE equals 00 (longword), and
DSIZE equals 01 (byte). Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed
on destination registers. The access sequence is as follows:
1. Read byte from 0x0001—write 1 byte, increment SAR
n
.
2. Read word from 0x0002—write 2 bytes, increment SAR
n
.
3. Read longword from 0x0004—write 4 bytes, increment SAR
n
.
4. Repeat longwords until SAR
n
= 0x00F0.
5. Read byte from 0x00F0—write byte, increment SAR
n
.
If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address,
but not exceeding the configured size.
16.4.4.2
Bandwidth Control
Bandwidth control makes it possible to force the DMA off the bus to allow access to another device.
DCR
n
[BWC] provides seven levels of block transfer sizes. If the BCR
n
decrements to a multiple of the
decode of the BWC, the DMA bus request negates until the bus cycle terminates. If a request is pending,
the arbiter may then pass bus mastership to another device. If auto-alignment is enabled,
DCR
n
[AA] equals 1, the BCR
n
may skip over the programmed boundary, in which case, the DMA bus
request is not negated.
