EzPort
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
18-5
Preliminary
18.4.1.4
Write Configuration Register
The Write Configuration Command updates the flash controller’s clock configuration register. The clock
configuration register divides down the flash controller’s internal system clock to a 150 kHz to 200 kHz
clock. This register must be initialized before any erase or program commands are issued to the flash
controller.
This command should not be used if the write error flag is set, a write is in progress, or the configuration
register has already been loaded (as it is a write-once register).
5
CRL
Configuration Register Loaded. Status flag that indicates if the configuration register has been loaded. The
configuration register initializes the flash controllers clock configuration register to generate a divided down
clock from the system clock that runs at a frequency of 150 kHz to 200 kHz. This register must be initialized
before any erase or program commands are accepted.
0 Configuration register has not been loaded; erase and program commands are not accepted.
1 Configuration register has been loaded; erase and program commands are accepted.
4–2
—
Reserved, should be cleared.
1
WEN
Write Enable. Control bit that must be set before a Write Configuration Register (WRCR), Page Program (PP),
Sector Erase (SE), or Bulk Erase (BE) command is accepted. Is set by the Write Enable (WREN) command
and cleared by reset or a Write Disable (WRDI) command. It also clears on completion of a write, erase, or
program command.
0 Disables the following write, erase, or program command.
1 Enables the following write, erase, or program command.
0
WIP
Write In Progress. Status flag that sets after a Write Configuration Register (WRCR), Page Program (PP),
Sector Erase (SE), or Bulk Erase (BE) command is accepted and clears after the flash memory erase or
program is completed. Only the Read Status Register (RDSR) command is accepted while a write is in
progress.
0 Write is not in progress. Accept any command.
1 Write is in progress. Only accept RDSR command.
IPSBAR
Offset:
Access: read/write
7
6
5
4
3
2
1
0
R
W
PRDIV8
DIV[5:0]
Reset:
0
0
0
0
0
0
0
0
Figure 18-3. EzPort Configuration Register
Table 18-3. EzPort Status Register Field Description (continued)
Field
Descriptions
