I
2
C Interface
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
24-2
Freescale Semiconductor
Preliminary
24.1.1
Block Diagram
is a block diagram of the I
2
C module.
Figure 24-1. I
2
C Module Block Diagram
shows the I
2
Section 24.2, “Memory Map/Register Definition”
:
•
I
2
C address register (I2ADR
n
)
•
I
2
C frequency divider register (I2FDR
n
)
•
I
2
C control register (I2CR
n
)
•
I
2
C status register (I2SR
n
)
•
I
2
C data I/O register (I2DR
n
)
24.1.2
Overview
I
2
C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. This bus is suitable for applications that require
occasional communication between many devices over a short distance. The flexible I
2
C bus allows
additional devices to connect to the bus for expansion and system development.
Address
Compare
In/Out
Data
Shift
Start, Stop,
Input
Sync
Clock
Control
Registers and Slave Interface
Address Decode
I
2
C Address
Data MUX
Address
IRQ
Data
and
Arbitration
Control
Register
Internal Bus
Register
(IADR)
I
2
C Frequency
Divider Register
(IFDR)
I
2
C Data
I/O Register
(I2DR)
I
2
C Status
Register
(I2SR)
I
2
C Control
Register
(I2CR)
SCL
SDA
