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Freescale Semiconductor MCF52100, Reference Manual

The Freescale Semiconductor MCF52100 is a versatile microcontroller ideal for embedded applications. You can find the Reference Manual for this product available for free download on our website. Get all the information you need to get started with your MCF52100 by visiting 88.208.23.73:8080.

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I

2

C Interface

MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1

Freescale Semiconductor

24-15

 

Preliminary

For a master receiver to terminate a data transfer, it must inform the slave transmitter by not 
acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last 
byte. Before the last byte is read, a STOP signal must be generated, as in the following example.

1. Decrement RXCNT.

2. If last byte (RXCNT = 0) go to step #4.

3. If next to last byte (RXCNT = 1), set I2CR[TXAK] to disable ACK and go to step #5.

4. This is last byte, so clear I2CR[MSTA] to generate a STOP signal.

5. Read data from I2DR.

6. If there is more data to be read (RXCNT

≠

0), go to step #1 if desired.

24.4.5

Generation of Repeated START

If the master wants the bus after the data transfer, it can signal another START followed by another slave 
address without signaling a STOP, as in the following example.

1. Generate a repeated START by setting I2CR[RSTA].

2. Transmit the calling address via I2DR.

24.4.6

Slave Mode

In the slave interrupt service routine, software must poll the I2SR[IAAS] bit to determine if the controller 
has received its slave address. If IAAS is set, software must set the transmit/receive mode select bit 
(I2CR[MTX]) according to the I2SR[SRW]. Writing to I2CR clears IAAS automatically. The only time 
IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred; 
interrupts resulting from subsequent data transfers have IAAS cleared. A data transfer can now be initiated 
by writing information to I2DR for slave transmits, or read from I2DR in slave-receive mode. A dummy 
read of I2DR in slave/receive mode releases SCL, allowing the master to send data.

In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data. Setting 
RXAK means an end-of-data signal from the master receiver, after which software must switch it from 
transmitter to receiver mode. Reading I2DR releases SCL so the master can generate a STOP signal.

24.4.7

Arbitration Lost

If several devices try to engage the bus at the same time, one becomes master. Hardware immediately 
switches devices that lose arbitration to slave receive mode. Data output to SDA stops, but SCL continues 
generating until the end of the byte during which arbitration is lost. An interrupt occurs at the falling edge 
of the ninth clock of this transfer with I2SR[IAL] equals 1 and I2CR[MSTA] equals 0.

If a device that is not a master tries to transmit or execute a START, hardware inhibits the transmission, 
clears MSTA without signaling a STOP, generates an interrupt to the CPU, and sets IAL to indicate a failed 
attempt to engage the bus. When considering these cases, slave service routine should first test IAL and 
software should clear it if it is set.

Summary of Contents for MCF52100

Page 1: ...MCF52110 ColdFire Integrated Microcontroller Reference Manual Devices Supported MCF52110 MCF52100 Document Number MCF52110RM Rev 1 06 2007...

Page 2: ...ny particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including w...

Page 3: ...t Timers PIT0 and PIT1 1 11 1 2 13 Real Time Clock RTC 1 11 1 2 14 Pulse Width Modulation PWM Timers 1 11 1 2 15 Software Watchdog Timer 1 12 1 2 16 Backup Watchdog Timer 1 12 1 2 17 Phase Locked Loop...

Page 4: ...se Address Registers RAMBAR FLASHBAR 3 8 3 3 Functional Description 3 8 3 3 1 Version 2 ColdFire Microarchitecture 3 8 3 3 2 Instruction Set Architecture ISA_A 3 14 3 3 3 Exception Processing Overview...

Page 5: ...1 PLL Mode 6 2 6 3 5 External Clock Mode 6 2 6 4 Low Power Mode Operation 6 2 6 5 Block Diagram 6 3 6 6 Signal Descriptions 6 4 6 6 1 EXTAL 6 5 6 6 2 XTAL 6 5 6 6 3 CLKOUT 6 5 6 6 4 CLKMOD 1 0 6 5 6...

Page 6: ...8 4 2 Peripheral Behavior in Low Power Modes 8 12 8 4 3 Summary of Peripheral State During Low Power Modes 8 15 Chapter 9 Chip Configuration Module CCM 9 1 Introduction 9 1 9 1 1 Features 9 1 9 2 Ext...

Page 7: ...1 15 Chapter 12 System Control Module SCM 12 1 Introduction 12 1 12 2 Overview 12 1 12 3 Features 12 1 12 4 Memory Map and Register Definition 12 2 12 5 Register Descriptions 12 3 12 5 1 Internal Peri...

Page 8: ...Registers IPRHn IPRLn 14 6 14 3 2 Interrupt Mask Register IMRHn IMRLn 14 7 14 3 3 Interrupt Force Registers INTFRCHn INTFRCLn 14 8 14 3 4 Interrupt Request Level Register IRLRn 14 10 14 3 5 Interrupt...

Page 9: ...nel Initialization and Startup 16 13 16 4 4 Data Transfer 16 14 16 4 5 Termination 16 15 Chapter 17 ColdFire Flash Module CFM 17 1 Introduction 17 1 17 1 1 Overview 17 1 17 1 2 Features 17 2 17 2 Exte...

Page 10: ...20 5 Signal Description 20 3 20 5 1 GPT 2 0 20 3 20 5 2 GPT3 20 3 20 5 3 SYNCn 20 4 20 6 Memory Map and Registers 20 4 20 6 1 GPT Input Capture Output Compare Select Register GPTIOS 20 5 20 6 2 GPT Co...

Page 11: ...9 4 Timer Overflow TOF 20 22 Chapter 21 DMA Timers DTIM0 DTIM3 21 1 Introduction 21 1 21 1 1 Overview 21 1 21 1 2 Features 21 2 21 2 Memory Map Register Definition 21 2 21 2 1 DMA Timer Mode Registers...

Page 12: ...1 2 Features 23 2 23 2 External Signal Description 23 3 23 3 Memory Map Register Definition 23 3 23 3 1 UART Mode Registers 1 UMR1n 23 5 23 3 2 UART Mode Register 2 UMR2n 23 6 23 3 3 UART Status Regis...

Page 13: ...9 24 3 3 Data Transfer 24 9 24 3 4 Acknowledge 24 10 24 3 5 STOP Signal 24 10 24 3 6 Repeated START 24 10 24 3 7 Clock Synchronization and Arbitration 24 12 24 3 8 Handshaking and Clock Stretching 24...

Page 14: ...t Sources 25 32 25 5 8 Power Management 25 32 25 5 9 ADC Clock 25 34 25 5 10Voltage Reference Pins VREFH and VREFL 25 37 25 5 11Supply Pins VDDA and VSSA 25 38 Chapter 26 Pulse Width Modulation PWM Mo...

Page 15: ...Background Debug Mode BDM 27 19 27 5 1 CPU Halt 27 19 27 5 2 BDM Serial Interface 27 20 27 5 3 BDM Command Set 27 22 27 6 Real Time Debug Support 27 39 27 6 1 Theory of Operation 27 39 27 6 2 Concurre...

Page 16: ...ss Register 28 5 28 3 4 JTAG_CFM_CLKDIV Register 28 5 28 3 5 TEST_CTRL Register 28 5 28 3 6 Boundary Scan Register 28 5 28 4 Functional Description 28 6 28 4 1 JTAG Module 28 6 28 4 2 TAP Controller 2...

Page 17: ...ntrol applications This 32 bit device is based on the Version 2 V2 ColdFire reduced instruction set computing RISC core with a multiply accumulate unit MAC and divider providing 76 Dhrystone 2 1 MIPS...

Page 18: ...tic RAM SRAM 64 16 Kbytes 128 16 Kbytes Interrupt Controller INTC Fast Analog to Digital Converter ADC Real Time Clock RTC Four channel Direct Memory Access DMA Software Watchdog Timer WDT Backup Watc...

Page 19: ...PU 4 CH JTAG TAP 16 Kbytes SRAM 2K 32 2 128 Kbytes flash memory 16K 16 4 PORTS CIM_IBO RSTI RSTO ADC AN 7 0 PLL OCO CLKGEN Edge Port TIM EXTAL XTAL CLKOUT PIT0 PIT1 PWM IRQ 7 1 PMM VSTBY PADI Pin Muxi...

Page 20: ...ution path Background debug mode BDM for in circuit debugging DEBUG_B Real time debug support with six hardware breakpoints 4 PC 1 address and 1 data configurable into a 1 or 2 level trigger On chip m...

Page 21: ...chip selects available Master mode operation only Programmable bit rates up to half the CPU clock frequency Up to 16 pre programmed transfers Fast analog to digital converter ADC Eight analog input c...

Page 22: ...reached PWM counter reaches zero or when the channel is disabled Programmable center or left aligned outputs on individual channels Four clock sources A B SA and SB provide for a wide range of freque...

Page 23: ...transfer support with 8 16 and 32 bit data capability along with support for 16 byte 4 32 bit burst transfers Source destination address pointers that can increment or remain constant 24 bit byte tran...

Page 24: ...Debug Module The ColdFire processor core debug interface is provided to support system debugging with low cost debug and emulator development tools Through a standard debug interface access to debug i...

Page 25: ...1 2 4 1 SRAM The dual ported SRAM module provides a general purpose 16 Kbyte memory block that the ColdFire core can access in a single cycle The location of the memory block can be set to any 16 Kbyt...

Page 26: ...iminating the need for an external clock source On smaller packages the third UART is multiplexed with other digital I O functions 1 2 7 I2 C Bus The MCF52110 includes two I2 C modules The I2C bus is...

Page 27: ...sting of a 16 bit programmable counter driven by a seven stage programmable prescaler Each of the four channels can be configured for input capture or output compare Additionally channel three can be...

Page 28: ...tdown The backup watchdog timer can be clocked by either the relaxation oscillator or the system clock 1 2 17 Phase Locked Loop PLL The clock module contains a crystal oscillator 8 MHz on chip relaxat...

Page 29: ...D JTAG Control of the LVD and its associated reset and interrupt are managed by the reset controller Other registers provide status flags indicating the last source of reset and a control bit for soft...

Page 30: ...Overview MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 1 14 Freescale Semiconductor Preliminary...

Page 31: ...t or output defines its state at reset and identifies whether a pull up resistor should be used NOTE The terms assertion and negation are used to avoid confusion when dealing with a mixture of active...

Page 32: ...TAG TAP 16 Kbytes SRAM 2K 32 2 128 Kbytes flash memory 16K 16 4 PORTS CIM_IBO RSTI RSTO ADC AN 7 0 PLL OCO CLKGEN Edge Port TIM EXTAL XTAL CLKOUT PIT0 PIT1 PWM IRQ 7 1 PMM VSTBY PADI Pin Muxing AN Sla...

Page 33: ...PIO Low FAST 52 G9 34 AN5 GPIO Low FAST 53 G8 35 AN4 GPIO Low FAST 54 F9 36 AN3 GPIO Low FAST 46 G7 28 AN2 GPIO Low FAST 45 G6 27 AN1 GPIO Low FAST 44 H6 26 AN0 GPIO Low FAST 43 J6 25 SYNCA3 N A N A S...

Page 34: ...N A N A pull up5 79 B7 50 TDO DSO High FAST 80 A7 51 TMS BKPT N A N A pull up5 76 A8 49 TRST DSCLK N A N A pull up5 85 B6 54 Mode Selection6 CLKMOD0 N A N A pull down6 40 G5 24 CLKMOD1 N A N A pull do...

Page 35: ...SR 23 PSRR 23 pull up9 62 D8 43 GPT2 PWM5 GPIO PDSR 22 PSRR 22 pull up9 61 D9 42 GPT1 PWM3 GPIO PDSR 21 PSRR 21 pull up9 59 E9 41 GPT0 PWM1 GPIO PDSR 20 PSRR 20 pull up9 58 F7 40 Timers 32 bit DTIN3 D...

Page 36: ...ral Purpose I O chapter All programmable signals default to 2 mA drive and FAST slew rate in normal single chip mode 2 All signals have a pull up in GPIO mode 3 These signals are multiplexed on other...

Page 37: ...ble 2 3 PLL and Clock Signals Signal Name Abbreviation Function I O External Clock In EXTAL Crystal oscillator or external clock input except when the on chip relaxation oscillator is used I Crystal X...

Page 38: ...L in normal mode clock driven by crystal Table 2 6 External Interrupt Signals Signal Name Abbreviation Function I O External Interrupts IRQ 7 1 External interrupt sources I Table 2 7 Queued Serial Per...

Page 39: ...tion Function I O Transmit Serial Data Output UTXDn Transmitter serial data outputs for the UART modules The output is held high mark condition when the transmitter is disabled idle or in the local lo...

Page 40: ...eference VRH Reference voltage high and low inputs I VRL I Analog Supply VDDA Isolate the ADC circuitry from power supply noise VSSA Table 2 12 GPT Signals Signal Name Abbreviation Function I O Genera...

Page 41: ...has been seen as high logic 1 I Development Serial Output DSO Development Serial Output Provides serial output communication for debug module responses DSO is registered internally The output is delay...

Page 42: ...ons Signal Name Abbreviation Function I O EzPort Clock EZPCK Shift clock for EzPort transfers I EzPort Chip Select EZPCS Chip select for signaling the start and end of serial transfers I EzPort Serial...

Page 43: ...1 Overview As with all ColdFire cores the V2 ColdFire core is comprised of two separate pipelines decoupled by an instruction buffer Figure 3 1 V2 ColdFire Core Pipelines The instruction fetch pipelin...

Page 44: ...s not empty the IFP stores the contents of the fetch cycle in the IB until it is required by the OEP For register to register and register to memory store operations the instruction passes through bot...

Page 45: ...0x081 Store 0x181 Data Register 1 D1 32 R W 0x10A0_1070 No 3 2 1 3 4 Load 0x082 7 Store 0x182 7 Data Register 2 7 D2 D7 32 R W Undefined No 3 2 1 3 4 Load 0x088 8E Store 0x188 8E Address Register 0 6...

Page 46: ...he user stack pointer USP The hardware implementation of these two programmable visible 32 bit registers does not identify one as the SSP and the other as the USP Instead 0xC05 RAM Base Address Regist...

Page 47: ...tecture to load store the USP move l Ay USP move to USP move l USP Ax move from USP These instructions are described in the ColdFire Family Programmer s Reference Manual NOTE The USP must be initializ...

Page 48: ...VBR are BDM LSB of Status Register SR Access User read write BDM read write 7 6 5 4 3 2 1 0 R 0 0 0 X N Z V C W Reset 0 0 0 Figure 3 5 Condition Code Register CCR Table 3 2 CCR Field Descriptions Fie...

Page 49: ...ded explicitly after reset and before any compare CMP Bcc or Scc instructions execute BDM 0x801 VBR Access Supervisor read write BDM read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13...

Page 50: ...lines is shown 10 8 I Interrupt level mask Defines current interrupt level Interrupt requests are inhibited for all priority levels less than or equal to current level except edge sensitive level 7 re...

Page 51: ...tage and the resulting prefetch address gated onto the core bus if there are no pending operand memory accesses which are assigned a higher priority After the prefetch address is driven onto the core...

Page 52: ...OEP for three basic classes of non branch instructions Register to register op Ry Rx Embedded load op mem y Rx Register to memory store move Ry mem x For simple register to register instructions the f...

Page 53: ...uired register operand is simultaneously fetched OC from the RGF Finally in the fourth cycle the instruction is executed EX The heavily used 32 bit load instruction move l mem y Rx is optimized to sup...

Page 54: ...multaneously allowing single cycle execution See Figure 3 14 where the effective address is of the form ea x d16 Ax i e a 16 bit signed displacement added to a base register Ax For read modify write i...

Page 55: ...diagrams of Figure 3 15 depict the execution templates for these three classes of instructions In these diagrams the x axis represents time and the various instruction operations are shown progressin...

Page 56: ...guage code Table 3 4 summarizes the instructions added to revision ISA_A to form revision ISA_A For more details see the ColdFire Family Programmer s Reference Manual Table 3 4 Instruction Enhancement...

Page 57: ...interrupt controller The IACK cycle is mapped to special locations within the interrupt controller s address space with the interrupt level encoded in the address 3 The processor saves the current co...

Page 58: ...as the first instruction of an interrupt service routine which services multiple interrupt requests with different interrupt levels For more details see ColdFire Family Programmer s Reference Manual...

Page 59: ...zeros for all other exceptions See Table 3 7 The 8 bit vector number vector 7 0 defines the exception type and is calculated by the processor for all internal faults and represents the value supplied...

Page 60: ...instruction that generated the write Accordingly the PC contained in the exception stack frame merely represents the location in the program when the access error was signaled All programming model up...

Page 61: ...respectively ColdFire cores do not provide illegal instruction detection on the extension words on any instruction including MOVEC 3 3 4 4 Divide By Zero Attempting to divide by zero causes an except...

Page 62: ...s a STOP instruction where the immediate operand sets SR T hardware loads the SR and generates a trace exception The PC in the exception stack frame points to the instruction after the STOP and the SR...

Page 63: ...o the instruction address defined by the second longword operand within the stack frame 3 3 4 11 TRAP Instruction Exception The TRAP n instruction always forces an exception as part of its execution a...

Page 64: ...stem reset The hardware configuration information is loaded immediately after the reset in signal is negated This allows an emulator to read out the contents of these registers via the BDM to determin...

Page 65: ...his bit signals if the optional floating point FPU execution engine is present in processor core 0 FPU execute engine not present in core This is the value used for this device 1 FPU execute engine is...

Page 66: ...associativity 00 Four way 01 Direct mapped This is the value used for this device Else Reserved for future use 27 24 CCSZ Configurable cache size Indicates the amount of instruction data cache The cac...

Page 67: ...words at the beginning of each instruction execution This implies that the OEP does not wait for the IFP to supply opwords and or extension words The OEP does not experience any sequence related pipe...

Page 68: ...mings for MOVE L NOTE For all tables in this section the execution time of any instruction using the PC relative effective addressing modes is the same for the comparable An relative mode The nomencla...

Page 69: ...2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 Ay 2 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 Ay 2 1 0 2 1 1 2 1 1 2 1 1 2 1 1 3 1 1 2 1 1 d16 Ay 2 1 0 2 1 1 2 1 1 2 1 1 2 1 1 d8 Ay Xi SF 3 1 0 3 1 1 3 1 1 3 1 1 xxx w...

Page 70: ...d8 An Xn SF d8 PC Xn SF xxx wl xxx add l ea Rx 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 add l Dy ea 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 addi l imm Dx 1 0 0 addq l imm ea 1 0 0 3 1 1 3 1 1 3 1 1...

Page 71: ...m Dx 1 0 0 lea ea Ax 1 0 0 1 0 0 2 0 0 1 0 0 lsl l ea Dx 1 0 0 1 0 0 lsr l ea Dx 1 0 0 1 0 0 moveq l imm Dx 1 0 0 or l ea Rx 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 or l Dy ea 3 1 1 3 1 1 3 1...

Page 72: ...ea 5 2 0 5 2 0 1 n is the number of registers moved by the MOVEM opcode 2If a MOVE W imm SR instruction is executed and imm 13 equals 1 the execution time is 1 0 0 3 The execution time for STOP is the...

Page 73: ...0 7 1 0 muls w ea y Dx 3 0 0 5 1 0 5 1 0 5 1 0 5 1 0 6 1 0 5 1 0 3 0 0 mulu l ea y Dx 5 0 0 7 1 0 7 1 0 7 1 0 7 1 0 mulu w ea y Dx 3 0 0 5 1 0 5 1 0 5 1 0 5 1 0 6 1 0 5 1 0 3 0 0 1 Effective address...

Page 74: ...ntegrated Microcontroller Reference Manual Rev 1 3 32 Freescale Semiconductor Preliminary Table 3 19 Bcc Instruction Execution Times Opcode Forward Taken Forward Not Taken Backward Taken Backward Not...

Page 75: ...Multiply accumulate operations supporting signed and unsigned integer operands as well as signed fixed point fractional operands 3 Miscellaneous register operations The MAC features a three stage exec...

Page 76: ...nite impulse response IIR filter A finite impulse response FIR filter can be obtained by setting coefficients a k to zero In either case the operations involved in computing such a filter are multipli...

Page 77: ...ls rounding while storing the accumulator to a general purpose register 0 Move accumulator without rounding to a 16 bit value Accumulator is moved to a general purpose register as a 32 bit value 1 The...

Page 78: ...ing convolution or any routine that implements a data array as a circular queue For MAC MOVE operations the MASK contents can optionally be included in all memory effective address calculations The sy...

Page 79: ...ueue implementations Figure 4 3 Mask Register MASK 4 2 3 Accumulator Register ACC The accumulator registers store 32 bits of the MAC operation result The accumulator extension registers form the entir...

Page 80: ...operands is a 32 bit result For longword integer operations only the least significant 32 bits of the product are calculated For fractional operations the entire 64 bit product is calculated and then...

Page 81: ...umber is rounded to the closest 16 bit number possible Let the high order 16 bits of R0 be named R0 U and the low order 16 bits be R0 L If R0 L is less than 0x8000 the result is truncated to the value...

Page 82: ...ce type can correctly save and restore the exact state of the MAC programming model 4 3 1 3 MULS MULU MULS and MULU are unaffected by fractional mode operation operands remain assumed to be integers 4...

Page 83: ...the largest negative number that can be represented is 1 whose internal representation is 0x8000 and 0x8000_0000 respectively The largest positive word is 0x7FFF or 1 2 15 the most positive longword...

Page 84: ...r the product is zero in which case a zero is shifted in For all left shifts a zero is inserted into the lsb position The following pseudocode explains basic MAC or MSAC instruction functionality This...

Page 85: ...duct 63 1 then result 31 0 0x8000_0000 else result 31 0 0x7fff_ffff else product 31 0 product 30 0 0 break case 2 reserved encoding break case 3 SF 1 if MACSR OMC 0 MACSR V 0 then product 31 0 product...

Page 86: ...for product rounding if MACSR R T 1 then perform convergent rounding if product 31 0 0x8000_0000 then product 63 32 product 63 32 1 else if product 31 0 0x8000_0000 product 32 1 then product 63 32 pr...

Page 87: ...31 0 check for product overflow if product 63 32 0x0000_0000 then product overflow MACSR V 1 if inst MSAC MACSR OMC 1 then result 31 0 0x0000_0000 else if MACSR OMC 1 then overflowed MAC saturationMo...

Page 88: ...else result 31 0 acc 31 0 product 31 0 check for accumulation overflow if accumulationOverflow 1 then MACSR V 1 if inst MSAC MACSR OMC 1 then result 31 0 0x0000_0000 else if MACSR OMC 1 then overflow...

Page 89: ...em stack Because the SRAM module is physically connected to the processor s high speed local bus it can service processor initiated accesses or memory referencing commands from the debug module The SR...

Page 90: ...everal control fields These fields are shown in Figure 5 1 Table 5 1 SRAM Programming Model Rc 11 0 1 1 The values listed in this column represent the Rc field used when accessing the core registers v...

Page 91: ...M When this bit is set any attempted write access from the core generates an access error exception to the ColdFire processor core 0 Allows core read and write accesses to the SRAM module 1 Allows onl...

Page 92: ...f the SRAM at 0x2000_0000 and initializes the SRAM to zeros RAMBASE EQU 0x20000000 set this variable to 0x20000000 RAMVALID EQU 0x00000001 move l RAMBASE RAMVALID D0 load RAMBASE valid bit into D0 mov...

Page 93: ...laxation oscillator or external oscillator reference options 2 to 10 MHz reference crystal oscillator for normal PLL mode External RTC backup oscillator nominal frequency 32 768 kHz System can be cloc...

Page 94: ...frequency equal to the external clock input reference frequency The post divider is not active 6 3 5 External Clock Mode In external clock mode the PLL is bypassed and the external clock is applied to...

Page 95: ...up period to restart When the PLL is enabled in stop mode STPMD 1 0 the external CLKOUT signal can support systems using CLKOUT as the clock source There is also a fast wakeup option for quickly enabl...

Page 96: ...ion refer to Chapter 2 Signal Descriptions EXTOSC OCOSC OCOSC CRYOSC EXTAL XTAL PLLMODE PLLEN CLKSRC PLL Low Power Divider LPD 3 0 Reference Clock 0 0 1 1 ADC auto standby clock OSCILLATOR ON CHIP 8MH...

Page 97: ...clock mode during chip configuration as described in Table 6 3 6 6 5 RSTO The RSTO pin is asserted by one of the following Internal system reset signal Table 6 2 Signal Properties Name Function EXTAL...

Page 98: ...reset value for ROCR is loaded during reset from the flash information row bits 9 0 The bits reset to 0b10_0000_0000 during Power On Reset 6 7 1 3 6 11 0x12_0007 Low Power Divider Register LPDR 8 R W...

Page 99: ...enabled when the device emerges from reset PLLMODE PLLEN1 W Reset 0 0 0 0 0 0 1 0 Figure 6 2 Synthesizer Control Register SYNCR Table 6 5 SYNCR Field Descriptions Field Description 15 LOLRE Loss of l...

Page 100: ...in MFD bit description Changing RFD 2 0 does not affect the PLL or cause a relock delay Changes in clock frequency are synchronized to the next falling edge of the current system clock To avoid surpas...

Page 101: ...t allows the PLL to first be enabled and then the system clock can be switched to the PLL output clock only after the PLL has locked When disabling the PLL the clock can be switched before disabling t...

Page 102: ...tion In external clock mode LOCKS remains cleared after reset In normal PLL mode and 1 1 PLL mode LOCKS is set after reset 3 LOCK Set when the PLL is locked PLL lock occurs when the synthesized freque...

Page 103: ...rdless if the reference clock or PLL clock is driving the system clock by a factor of 2n where n is a number from 0 to 15 represented by the 4 bit field The clock change takes effect with the next ris...

Page 104: ...When switching clock sources the module ensures that the changeover does not cause spurious glitches in the system clock and that the crystal and the relaxation oscillator remain enabled for the dura...

Page 105: ...es from the external oscillator 1 PLL input bypass clock comes from the relaxation oscillator Note When switching clock sources the module ensures that during the changeover no spurious glitches occur...

Page 106: ...illator 0 Relaxation oscillator is disabled 1 Relaxation oscillator is enabled Note When switching the clock source to the relaxation oscillator this bit should be set before CCLR OSCSEL is set 6 STBY...

Page 107: ...rnal crystal mode 5 LPEN Low Power Enable bit This bit configures the external oscillator to run in low power mode when using an external crystal 0 External oscillator runs in normal power mode 1 Exte...

Page 108: ...oscillator mode 1 RTC oscillator is running in external crystal mode 1 LPEN Low Power Enable bit This bit configures the RTC oscillator to run in low power mode when using an external crystal 0 RTC os...

Page 109: ...ck mode the system is static and does not recognize reset until a clock is generated from the reference clock source selected by the CLKMOD pins see Section 6 6 4 CLKMOD 1 0 1 BWDSTOP This bit determi...

Page 110: ...ged 1 Determine the appropriate value for the MFD and RFD fields in the SYNCR The amount of jitter in the system clocks can be minimized by selecting the maximum MFD factor that can be paired with an...

Page 111: ...edge of the feedback clock leads the falling edge of the reference clock the PFD pulses the DOWN signal The width of these pulses relative to the reference clock depends on how much the two clocks lea...

Page 112: ...y to determine when frequency lock is achieved Phase lock is inferred by the frequency relationship but is not guaranteed The LOCK flag in the SYNSR reflects the PLL lock status A sticky lock flag LOC...

Page 113: ...op mode the LOCKS flag reflects the value prior to entering stop mode after lock is regained 6 8 4 7 PLL Loss of Lock Reset If the LOLRE bit in the SYNCR is set a loss of lock condition asserts reset...

Page 114: ...e remaining operational clock The alternate clock source generates the system clocks until reset is asserted As Table 6 18 shows if the reference fails the PLL goes out of lock and into self clocked m...

Page 115: ...ck Stuck NRM 0 0 0 Off Off 0 Lose lock f b clock reference clock Regain NRM LK 1 LC No regain Stuck NRM X 0 0 Off Off 1 Lose lock f b clock reference clock Regain clocks but don t regain lock SCM unst...

Page 116: ...N 0 NRM 0 0 0 On On 1 NRM LK 1 LC Lose lock Unstable NRM 0 0 1 LC Lose lock regain NRM 0 1 LC Lose clock Stuck Lose clock regain without lock Unstable NRM 0 0 1 LC Lose clock regain with lock NRM 0 1...

Page 117: ...akeup without lock NRM 1 0 0 On On 0 NRM LK 1 LC Lose reference clock SCM 0 0 1 Wakeup without lock Lose f b clock REF 0 X 1 Wakeup without lock Lose lock Stuck Lose lock regain NRM 0 1 LC NRM 1 0 0 O...

Page 118: ...1 LC Lose lock regain NRM 0 1 LC NRM 1 1 1 On On X NRM LK 1 LC Lose clock or lock RESET Reset immediately REF 1 0 0 X X X REF 0 X 1 Lose reference clock Stuck SCM 1 0 0 Off X 0 PLL disabled Regain SCM...

Page 119: ...e mode due to losing PLL clock or lock from NRM mode SCM PLL self clocked mode due to losing reference clock from NRM mode RESET immediate reset LOCKS LK expecting previous value of LOCKS before enter...

Page 120: ...Clock Module MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 6 28 Freescale Semiconductor Preliminary...

Page 121: ...way code It incorporates a free running down counter that generates a warm reset on underflow To prevent a reset software must periodically restart the countdown by writing a special set of values to...

Page 122: ...TOP 0 the BWT continues to operate normally when the device enters Stop mode 7 2 Memory Map and Register Definition The backup watchdog timer programming model includes registers in the BWT and clock...

Page 123: ...preserved during warm resets 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Figure 7 2 Backup Watchdog Timer Control Register WCR Table 7 2 WCR Field Descriptions Field Description 15 5 Reserved should read 0 Write...

Page 124: ...7 2 2 3 Backup Watchdog Timer Count Register WCNTR The WCNTR shown in Figure 7 4 reflects the current value in the BWT counter This counter is reset to the value in WMR when the BWT is serviced WCNTR...

Page 125: ...ore the timeout period is reached to prevent a reset Writing any values other than 0x5555 or 0xAAAA to the WSR resets the servicing sequence The software must then begin the sequence again writing 0x5...

Page 126: ...uard against runaway code The following procedure summarizes how to enable and service the BWT properly 1 Select the desired clock source for the BWT from within the clock module see Chapter 6 Clock M...

Page 127: ...on Register Width bits Access Reset Value Section Page 0x11_0004 Chip Configuration Register CCR 2 2 The CCR is described in the Chip Configuration Module It is shown here only to warn against acciden...

Page 128: ...SCM are fundamental to the operation of the system the clocks for these three modules cannot be disabled The individual bits of the PPMRx can be modified using a read modify write to this register di...

Page 129: ...bit general purpose timer module GPT 0 ICOC module clock is enabled 1 ICOC module clock is disabled 7 CDADC Disable clock to the ADC module 0 ADC module clock is enabled 1 ADC module clock is disabled...

Page 130: ...0 0 1 0 0 0 Figure 8 2 Peripheral Power Management Register Low PPMRL Table 8 3 PPMRL Field Descriptions Field Description 31 18 Reserved should be cleared 17 CDINTC0 Disable clock to the INTC0 module...

Page 131: ...The LPICR is programmed setting the ENBSTOP bit if stop mode is the desired low power mode and loading the appropriate interrupt priority level 10 CDQSPI Disable clock to the QSPI module 0 QSPI module...

Page 132: ...w power modes such as doze or wait fixed or programmable interrupts may be used however the module generating the interrupt must be enabled in that particular low power mode 5 After an appropriately h...

Page 133: ...PS module without the need to perform a read modify write on the PPMRx The data value on a register write causes the corresponding bit in the PPMRx register to be cleared A data value of 64 to 127 pro...

Page 134: ...It specifies the low power mode entered when the STOP instruction is issued and controls clock activity in this low power mode IPSBAR Offset 0x0022 PPMRC Access write only 7 6 5 4 3 2 1 0 R 0 W PPMRC...

Page 135: ...ode select Used to select the low power mode the chip enters after the ColdFire CPU executes the STOP instruction These bits must be written prior to instruction execution for them to take effect The...

Page 136: ...internal clocks appropriately During stop mode the system clock is stopped low For entry into stop mode the LPICR ENBSTOP bit must be set before a STOP instruction is issued IPSBAR Offset 0x0023 IPSBM...

Page 137: ...ected In this mode peripherals may be programmed to continue operating and can generate interrupts which cause the CPU to exit from wait mode 8 4 1 3 Doze Mode Doze mode affects the CPU in the same ma...

Page 138: ...wer mode 8 4 2 4 DMA Controller DMA0 DMA3 In wait and doze modes the DMA controller is capable of bringing the device out of a low power mode by generating an interrupt upon completion of a transfer o...

Page 139: ...to the low power mode entry 8 4 2 8 DMA Timers DTIM0 DTIM3 In wait and doze modes the DMA timers may generate an interrupt to exit a low power mode This interrupt can be generated when the DMA Timer i...

Page 140: ...a watchdog timer timeout may generate a reset to exit these low power modes When the CPU is inactive a software reset cannot be generated to exit any low power mode 8 4 2 12 Chip Configuration Module...

Page 141: ...ller logic is clocked using the TCLK input and is not affected by the system clock The JTAG cannot generate an event to cause the CPU to exit any low power mode Toggling TCLK during any low power mode...

Page 142: ...ed Yes2 Program Yes2 Stopped No General Purpose Timer Enabled Yes2 Enabled Yes2 Stopped No PWM Program No Program No Stopped No BDM Enabled Yes4 Enabled Yes4 Enabled Yes4 JTAG Enabled No Enabled No En...

Page 143: ...et are Operating Mode Serial flash programming mode EzPort mode Single chip mode Clock Reference External oscillator External crystal On chip 8 MHz oscillator Phase locked look PLL BDM or JTAG mode 9...

Page 144: ...nal is used to select between debug module JTAG_EN 0 and JTAG JTAG_EN 1 modes at reset 9 2 4 TEST Reserved for factory testing only In normal modes of operation this pin must be connected to VSS to av...

Page 145: ...e only to warn against accidental writes to this register 8 R W 0x00 8 2 5 8 8 0x11_0008 Reset Configuration Register RCON 16 R 0x0000 9 3 3 2 9 4 0x11_000A Chip Identification Register CIR 16 R See n...

Page 146: ...Table 9 5 RCON Field Descriptions Field Description 15 6 Reserved should be cleared 5 RLOAD Pad Driver Load This read only field reflects the reset value of the pin drive strength register If booting...

Page 147: ...minary Table 9 6 CIR Field Description Field Description 15 6 PIN Part identification number Contains a unique identification number for the device 5 0 PRN Part revision number This number is increase...

Page 148: ...Chip Configuration Module CCM MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 9 6 Freescale Semiconductor Preliminary...

Page 149: ...terrupts and resets is implemented within the reset controller module 10 2 Features Module features include the following Seven sources of reset External reset input Power on reset POR Watchdog timer...

Page 150: ...al is driven low when the internal reset controller module resets the chip When RSTO is active the user can drive override options on the data bus 10 5 Memory Map and Registers The reset controller pr...

Page 151: ...ield Description 7 SOFTRST Allows software to request a reset The reset caused by setting this bit clears this bit 1 Software reset request 0 No software reset request 6 FRCRSTOUT Allows software to a...

Page 152: ...VDRE LVD reset enable Controls the LVD reset if LVDE is set This bit has no effect if the LVDE bit is a logic 0 LVD reset has priority over LVD interrupt if both are enabled 1 LVD reset enabled 0 LVD...

Page 153: ...1 Last reset caused by software 0 Last reset not caused by software 4 Reserved should be cleared 3 POR Power on reset flag Indicates that the last reset was caused by a power on reset 1 Last reset ca...

Page 154: ...us cycle is completed The reset controller asserts RSTO for approximately 512 cycles after RSTI is negated and the PLL has acquired lock The part then exits reset and begins operation In low power sto...

Page 155: ...le Semiconductor 10 7 Preliminary 10 6 2 Reset Control Flow The reset logic control flow is shown in Figure 10 4 In this figure the control state boxes have been numbered and these numbers are referre...

Page 156: ...l Flow RSTI PIN OR WD TIMEOUT OR SW RESET LOSS OF CLOCK LOSS OF LOCK RSTI NEGATED PLL MODE BUS CYCLE COMPLETE RCON ASSERTED PLL LOCKED ENABLE BUS MONITOR ASSERT RSTO AND LATCH RESET STATUS WAIT 512 CL...

Page 157: ...ock 1 or loss of lock 2 the reset control logic asserts RSTO 4 The reset control logic waits for the PLL to attain lock 9 9A before waiting 512 CLKOUT cycles 1 Then the reset control logic may latch t...

Page 158: ...r loss of lock condition is detected while waiting for the current bus cycle to complete 5 6 for an external reset request the EXT SOFT and or WDR bits along with the LOC and or LOL bits are set If th...

Page 159: ...wing blocks Time of day TOD clock counter Alarm Minute stopwatch Associated control and bus interface hardware Figure 11 1 Real Time Clock Block Diagram 11 1 2 Features The RTC module includes the fol...

Page 160: ...occurs Minute Stopwatch The minute stopwatch performs a countdown with a one minute resolution It can be used to generate an interrupt on a minute boundary 11 2 Memory Map Register Definition The RTC...

Page 161: ...to the reset values shown in Figure 11 2 Figure 11 2 RTC Hours and Minutes Counter Register HOURMIN IPSBAR Offset 0x03C0 HOURMIN Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 162: ...et POR sets the RTC to the reset values shown in Figure 11 3 Figure 11 3 RTC Seconds Counter Register SECONDS IPSBAR Offset 0x03C4 SECONDS Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 163: ...TC Hours and Minutes Alarm Register ALRM_HM IPSBAR Offset 0x03C8 ALRM_HM Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0...

Page 164: ...itten at any time Figure 11 5 RTC Seconds Alarm Register ALRM_SEC IPSBAR Offset 0x03CC ALRM_SEC Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 165: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 EN 0 0 0 0 0 0 SWR W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Table 11 6 R...

Page 166: ...ur counter has incremented If enabled this bit is set on every increment of the RTC hour counter 0 No 1 hour interrupt occurred 1 A 1 hour interrupt has occurred 4 1HZ 1 Hz flag bit This bit indicates...

Page 167: ...The 1 hour interrupt id disabled 1 The 1 hour interrupt is enabled 4 1HZ 1 Hz interrupt enable bit This bit enables disables an interrupt when the second counter of the real time clock increments 0 T...

Page 168: ...7 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 CNT W Reset 0 0 0 0 0 0 0 0 0 0...

Page 169: ...changes to the new value This register cannot be reset because the real time clock is always enabled at reset Only 16 bit accesses to this register are allowed Figure 11 10 RTC Days Counter Register...

Page 170: ...re 11 12 RTC General Oscillator Count Upper Register RTCGOCU IPSBAR Offset 0x03E4 ALRM_DAY Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Re...

Page 171: ...the RTC This 1 Hz clock drives the RTC s counters The counter portion of the RTC module consists of four groups of counters that are physically located in three registers The 6 bit seconds counter is...

Page 172: ...e alarm should generate an interrupt When the TOD clock value and the alarm value coincide if the ALM bit in the real time clock interrupt enable register RTCIENR is set an interrupt occurs Please be...

Page 173: ...CCC MCF_RTCGOCL 0x00002000 32KHz MCF_CLOCK_RTCCR 0b01010111 RTCCC MCF_RTC_HOURMIN MCF_RTC_HOURMIN_HOURS uint32 time_temp 24 MCF_RTC_HOURMIN MCF_RTC_HOURMIN_MINUTES uint32 time_temp 60 MCF_RTC_SECONDS...

Page 174: ...Real Time Clock MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 11 16 Freescale Semiconductor Preliminary...

Page 175: ...upports two memory banks one for the internal SRAM and the other for the internal flash The SACU provides the mechanism needed to implement secure bus transactions to the system address space The prog...

Page 176: ...0x0011 Core Watchdog Control Register CWCR 8 R W 0x00 12 5 4 12 7 0x0012 Low Power Interrupt Control Register LPICR 8 R W 0x00 8 2 2 8 5 0x0013 Core Watchdog Service Register CWSR 8 R W 12 5 5 12 8 0...

Page 177: ...GPACR0 Register 8 R W 0x00 12 7 3 3 12 16 0x0031 GPACR1 Register 8 R W 0x00 12 7 3 3 12 16 1 Addresses not assigned to a register and undefined register bits are reserved for expansion 2 The PPMRH LPI...

Page 178: ...ccessed directly by the core and or other system bus masters Because this memory provides single cycle accesses at processor speed it is ideal for applications where double buffer schemes can be used...

Page 179: ...he RAMBAR is typically the same value however they can be programmed to different values By definition the base address must be a 0 modulo size value The SRAM modules are configured through the RAMBAR...

Page 180: ...n the reset is complete Only one bit is set at any one time in the CRSR The register reflects the cause of the most recent reset To clear a bit a logic 1 must be written to the bit location writing a...

Page 181: ...viced by performing the following sequence 1 Write 0x55 to CWSR 2 Write 0xAA to CWSR Both writes must occur in order before the time out but any number of instructions can be executed between the two...

Page 182: ...ed behavior results Note If a core reset is required the watchdog interrupt should set the soft reset bit in the interrupt controller 5 3 CWT 2 0 Core watchdog timing delay These bits select the timeo...

Page 183: ...pointed to by the current arbitration pointer may get on the bus with zero latency if the address phase is available All other requesters face at least a one cycle arbitration pipeline delay to meet b...

Page 184: ...of a transfer the master is given the lowest priority and the priority for all other masters is increased by one If no masters are requesting the arbitration unit must park pointing at one of the mast...

Page 185: ...rity of its bus requests 1 enable the use of the DMA s bandwidth control to elevate the priority of its bus requests 24 BCR24BIT Enables the use of 24 bit byte count registers in the DMA module 0 DMA...

Page 186: ...ter and another set of control registers define the access levels associated with the peripheral modules and memory space The SACU s programming model is physically implemented as part of the system c...

Page 187: ...at reset This is intended to support the concept of a trusted bus master and also controls the ability of a bus master to modify the register state of any of the SACU control registers that is only tr...

Page 188: ...rced to 1 at reset 12 7 3 2 Peripheral Access Control Registers PACR0 PACR8 Access to several on chip peripherals is controlled by shared peripheral access control registers A single PACR defines the...

Page 189: ...en platform peripheral The encodings for this field are shown in Table 12 11 3 LOCK0 This bit when set prevents subsequent writes to ACCESSCTRL0 Any attempted write to the PACR generates an error term...

Page 190: ...elect the specific GPACRn to be used for a given reference within the IPS address space These access control registers are 8 bits wide so that read write and execute attributes may be assigned to the...

Page 191: ...GPACR generates an error termination and the contents of the register are not affected Only a system reset clears this flag 6 4 Reserved should be cleared 3 0 ACCESS_CTRL This 4 bit field defines the...

Page 192: ...y Table 12 15 GPACR Address Space Register Space Protected IPSBAR Offset Modules Protected GPACR0 0x0000_0000 0x03FF_FFFF Ports CCM PMM Reset controller Clock EPORT WDOG PIT0 PIT3 QADC GPTA GPTB CFM C...

Page 193: ...ule Block Diagram DDATA 3 0 PDD 7 4 PORT QS PORT AS PORT DD PORT UA PORT UC PORT TC PORT TD PST 3 0 PDD 3 0 SDA0 PAS 1 URXD2 SCL0 PAS 0 UTXD2 QSPI_CLK PQS 2 SCL0 URTS1 QSPI_DIN PQS 1 SDA1 URXD1 QSPI_D...

Page 194: ...mers 13 3 Features The MCF52110 ports includes these distinctive features Control of primary function use on all ports Digital I O support for all ports registers for Storing output pin data Controlli...

Page 195: ...DDRAS S U 0x10_0024 DDRQS Reserved DDRTA DDRTC S U 0x10_0028 DDRTD DDRUA DDRUB DDRUC S U 0x10_002C DDRDD Reserved Reserved Reserved S U Port Pin Data Set Data Registers 0x10_0030 Reserved 0x10_0034 Re...

Page 196: ...re set Reading a PORTn register returns the current values in the register not the port n pin values PORTn bits can be set by setting the PORTn register or by setting the corresponding bits in the POR...

Page 197: ...s are read write At reset all bits in the DDRn registers are cleared IPSBAR Offset 0x10_000C PORTQS Access User read write 7 6 5 4 3 2 1 0 R 0 PORTn6 PORTn5 PORTn4 PORTn3 PORTn2 PORTn1 PORTn0 W Reset...

Page 198: ...0 Implemented DDRDD DDRAN IPSBAR Offsets 0x10_0026 DDRTA 0x10_0027 DDRTC 0x10_0028 DDRTD 0x10_0029 DDRUA 0x10_002A DDRUB 0x10_002B DDRUC Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 DDRn3 DDRn2 D...

Page 199: ...ORTnP SETn registers are set to the current pin states Reading a PORTnP SETn register returns the current state of the port n pins Writing 1s to a PORTnP SETn register sets the corresponding bits in t...

Page 200: ...ETTC PORTTD SETTD PORTUA SETUA PORTUB SETUB PORTUC SETUC IPSBAR Offset 0x10_003C PORTQSP SETQS Access User read write 7 6 5 4 3 2 1 0 R 0 PORTnP6 PORTnP5 PORTnP4 PORTnP3 PORTnP2 PORTnP1 PORTnP0 W Rese...

Page 201: ...n registers The CLRn registers are read write Table 13 4 PORTnP SETn Field Descriptions Field Description PortnPx Port nx pin data set data bits 1 PortnPx pin state is 1 read writing a 1 sets the corr...

Page 202: ...ccess User read write 7 6 5 4 3 2 1 0 R 0 CLRn6 CLRn5 CLRn4 CLRn3 CLRn2 CLRn1 CLRn0 W Reset 0 0 0 0 0 0 0 0 Figure 13 19 Port QS Clear Output Data Register CLRQS IPSBAR Offset 0x10_0050 CLRNQ Access U...

Page 203: ...lternate 2 tertiary and GPIO quaternary functions The fields are described in Table 13 7 which applies to all quad function registers IPSBAR Offsets 0x10_0074 PDDPAR 0x10_006A PANPAR Access User read...

Page 204: ...0 0 PnPAR1 PnPAR0 W Reset 0 0 0 0 0 0 0 0 Figure 13 25 Port AS Pin Assignment Register PASPAR IPSBAR Offsets 0x10_006E PTAPAR 0x10_006F PTCPAR 0x10_0070 PTDPAR 0x10_0071 PUAPAR 0x10_0072 PUBPAR Acces...

Page 205: ...he primary function IRQ instead of GPIO 13 6 6 Pad Control Registers 13 6 6 1 Pin Slew Rate Register PSRR The pin slew rate register PSRR is read write Each bit resets to logic 0 in Single Chip mode M...

Page 206: ...R23 PSRR22 PSRR21 PSRR20 PSRR19 PSRR18 PSRR17 PSRR16 W Reset 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 R PSRR15 PSRR14 PSRR13 PSRR12 PSRR11 PSRR10 PSRR9 PSRR8 W Reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 R PSR...

Page 207: ...DSR Access User read write 31 30 29 28 27 26 25 24 R PDSR31 PDSR30 PDSR29 PDSR28 PDSR27 PDSR26 PDSR25 PDSR24 W Reset See note 1 23 22 21 20 19 18 17 16 R PDSR23 PDSR22 PDSR21 PDSR20 PDSR19 PDSR18 PDSR...

Page 208: ...General Purpose I O Module MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 13 16 Freescale Semiconductor Preliminary...

Page 209: ...pt architecture of the 68K ColdFire family is appropriate The interrupt architecture of ColdFire is exactly the same as the M68000 family where there is a 3 bit encoded interrupt priority level sent f...

Page 210: ...he level of the interrupt being acknowledged effectively masking that level and all lower values while in the service routine For this device the processing of the interrupt acknowledge cycle is funda...

Page 211: ...2 Interrupt Prioritization As an active request is detected it is translated into the programmed interrupt level and the resulting 7 bit decoded priority level IRQ 7 1 is driven out of the interrupt c...

Page 212: ...vice 14 2 Memory Map The register programming model for the interrupt controllers is memory mapped to a 256 byte space In the following discussion there are a number of program visible registers great...

Page 213: ...x0C74 ICRn52 ICRn53 ICRn54 ICRn55 IPSBAR 0x0C78 ICRn56 ICRn57 ICRn58 ICRn59 IPSBAR 0x0C7C ICRn60 ICRn61 ICRn62 ICRn63 IPSBAR 0x0C80 IPSBAR 0x0CDC Reserved IPSBAR 0x0CE0 SWIACKn Reserved IPSBAR 0x0CE4...

Page 214: ...W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R INT 47 32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14 1 Interrupt Pending Register High IPRHn Table 14 3 IPRHn Fi...

Page 215: ...s the signal generated by the interrupting source The corresponding IPRLn bit reflects the state of the interrupt signal even if the corresponding IMRLn bit is set 0 The corresponding interrupt source...

Page 216: ...ed 14 3 3 Interrupt Force Registers INTFRCHn INTFRCLn The INTFRCHn and INTFRCLn registers each 32 bits provide a mechanism to allow software generation of interrupts for each possible source for funct...

Page 217: ...riptions Field Description 31 0 INTFRCH Interrupt force Allows software generation of interrupts for each possible source for functional or debug purposes 0 No interrupt forced on corresponding interr...

Page 218: ...register is also loaded with information about the interrupt level and priority being acknowledged This register provides the association between the acknowledged physical interrupt request number an...

Page 219: ...to program the ICRnx registers with unique and non overlapping level and priority definitions Failure to program the ICRnx registers in this manner can result in undefined behavior If a specific inter...

Page 220: ...can result in undefined behavior If a specific interrupt request is completely unused the ICRnx value can remain in its reset and disabled state Figure 14 9 Interrupt Control Register ICRnx Table 14...

Page 221: ...ervice complete 9 DMA DONE DMA Channel 0 transfer complete Write DONE 1 10 DONE DMA Channel 1 transfer complete Write DONE 1 11 DONE DMA Channel 2 transfer complete Write DONE 1 12 DONE DMA Channel 3...

Page 222: ...or access IC OC if TFFCA 1 45 C1F Timer channel 1 Write 1 to C1F or access IC OC if TFFCA 1 46 C2F Timer channel 2 Write 1 to C2F or access IC OC if TFFCA 1 47 C3F Timer channel 3 Write 1 to C3F or a...

Page 223: ...the overhead associated with interrupt exception processing including machine state save restore functions can be minimized In general the software IACK is performed near the end of an interrupt servi...

Page 224: ...exit from the low power stop mode This special mode of operation works as follows 1 LPICR 6 4 is loaded with the specified mask level while the core is in stop mode LPICR 7 must be set to enable this...

Page 225: ...ontroller enables a special logic path that evaluates the incoming interrupt sources in a purely combinatorial path that is there are no clocked storage elements If an active interrupt request is asse...

Page 226: ...Interrupt Controller Module MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 14 18 Freescale Semiconductor Preliminary...

Page 227: ...or a general purpose input output I O pin NOTE Not all EPORT signals may be output from the device See Chapter 2 Signal Descriptions to determine which signals are available Figure 15 1 EPORT Block D...

Page 228: ...is bypassed for the level detect logic because no clocks are available 15 3 Interrupt GPIO Pin Descriptions All EPORT pins default to general purpose input pins at reset The pin value is synchronized...

Page 229: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 15 2 EPORT Pin Assignment Register EPPAR Table 15 3 EPPAR Field Descriptions Field Description 15 2 EPPAn EPORT Pin Assignment Select Fields The read write EPPAn field...

Page 230: ...PDDR Field Descriptions Field Description 7 2 EPDDn Setting any bit in the EPDDR configures the corresponding pin as an output Clearing any bit in EPDDR configures the corresponding pin as an input Pi...

Page 231: ...negates any interrupt request from the corresponding EPORT pin Reset clears EPIE7 EPIE1 0 Interrupt requests from corresponding EPORT pin disabled 1 Interrupt requests from corresponding EPORT pin ena...

Page 232: ...write 7 6 5 4 3 2 1 0 R EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 0 W Reset 0 0 0 0 0 0 0 0 Figure 15 7 EPORT Port Flag Register EPFR Table 15 8 EPFR Field Descriptions Field Description 7 1 EPFn Edge port f...

Page 233: ...is used throughout this section to refer to registers or signals associated with one of the four identical DMA channels DMA0 DMA1 DMA2 or DMA3 16 1 1 Overview The DMA controller module enables fast tr...

Page 234: ...ddress transfers Channel arbitration on transfer boundaries Data transfers in 8 16 32 or 128 bit blocks using a 16 byte buffer Continuous mode or cycle steal transfers Independent transfer widths for...

Page 235: ...rs A dual address transfer consists of a read followed by a write and is initiated by an internal request using the START bit or by a peripheral DMA request Two types of transfer can occur a read from...

Page 236: ...ister 0 BCR0 and DMA Status Register 0 DSR0 0x00_010C DMA Control Register 0 DCR0 1 0x00_0110 Source Address Register 1 SAR1 0x00_0114 Destination Address Register 1 DAR1 0x00_0118 Byte Count Register...

Page 237: ...ical connection between the DMA requesters and that DMA channel There are ten possible requesters 4 DMA Timers and 6 UARTs Any request can be routed to any of the DMA channels Effectively the DMAREQC...

Page 238: ...A controller writes to the appropriate DSRn bit Only a write to DSRn DONE results in action DSRn DONE is set when the block transfer is complete When a transfer sequence is initiated and BCRn BCR is n...

Page 239: ...r occurred 1 The DMA channel terminated with a bus error during the write portion of a transfer 3 Reserved should be cleared 2 REQ Request 0 No request is pending or the channel is currently active Cl...

Page 240: ...condition 0 No interrupt is generated 1 Internal interrupt signal is enabled 30 EEXT Enable external request Care should be taken because a collision can occur between the START bit and DREQn when EEX...

Page 241: ...burst 19 DINC Destination increment Controls whether a destination address increments after each successful transfer 0 No change to the DAR after a successful transfer 1 The DAR increments by 1 2 4 o...

Page 242: ...led DMOD value is non zero the buffer base address is located on a boundary of the buffer size The value of this boundary depends on the initial destination address DAR The base address should be alig...

Page 243: ...channel LCH1 after each cycle steal transfer followed by a link to LCH2 after the BCR decrements to zero 10 Perform a link to channel LCH1 after each cycle steal transfer 11 Perform a link to channel...

Page 244: ...es bus control The DMA negates its internal bus request on the last transfer before BCRn reaches a multiple of the boundary specified in BWC Upon completion the DMA reasserts its bus request to regain...

Page 245: ...If the DCRn BWC value of sequential channels are equal the channels are prioritized in ascending order The DMAREQC register is configured to assign peripheral DMA requests to the individual DMA channe...

Page 246: ...is performed on registers not chosen for alignment If BCRn is greater than 16 the address determines transfer size Bytes words or longwords are transferred until the address is aligned to the programm...

Page 247: ...fer can terminate for one of the following reasons Error conditions When the DMA encounters a read or write cycle that terminates with an error condition DSRn BES is set for a read and DSRn BED is set...

Page 248: ...DMA Controller Module MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 16 16 Freescale Semiconductor Preliminary...

Page 249: ...xecutes read operations to the flash memory using one or two system bus cycles to access each flash physical block with access latency depending on the factory setting of the CLKSEL bits in the CFMCLK...

Page 250: ...er supply for program and erase operations Software programmable interrupts on command completion access violations or protection violations Fast page erase operation Fast word program operation Prote...

Page 251: ...AM_ARRAY_BASE 0000_0000 to PROGRAM_ARRAY_BASE 0001_FFFF Figure 17 2 CFM Flash Memory Map The CFM has hardware interlocks that protect data from accidental corruption using program or erase operations...

Page 252: ...ister contains several control fields These fields are shown in Figure 17 3 NOTE The default value of the FLASHBAR is determined by the chip configuration selected at reset see Chapter 9 Chip Configur...

Page 253: ...g internally in master mode RCON asserted and D 26 D 17 D 16 are set to 111 and D 18 and D 19 are set to 00 See Chapter 9 Chip Configuration Module CCM for more details When the default reset configur...

Page 254: ...cleared 5 1 C I SC SD UC UD Address Space Masks ASn These five bit fields allow certain types of accesses to be masked or inhibited from accessing the flash module The address space mask bits are C I...

Page 255: ...locations generate a cycle termination transfer error IPSBAR Offset 0x1D_0000 CFMMCR Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 LOCK PVIE AEIE CBEI E CCIE KEYA CC 0 0 0...

Page 256: ...MUSTAT register is set 1 An interrupt is requested when the CBEIF flag is set 0 CBEIF interrupt disabled 6 CCIE Command Complete Interrupt Enable The CCIE bit is always readable and writable The CCIE...

Page 257: ...es the internal flash bus clock down to a frequency of 150 KHz 200 KHz The internal flash bus clock frequency range is 150 KHz less than the internal flash bus clock which is less than 102 4 MHz The C...

Page 258: ...own in f helvetica st bold Figure 17 8 29 16 Reserved should read 0 15 0 SEC Flash memory security bits The SEC bits define the security state of the MCU as shown in Table 17 7 which defines the singl...

Page 259: ...re 17 8 CFMPROT Protection Diagram Table 17 8 CFMPROT Field Descriptions Field Description 31 0 PROTECT Each flash logical sector can be protected from program and erase operations by setting the PROT...

Page 260: ...ash configuration field must first be unprotected and then the flash supervisor access bytes must be programmed with the desired value Each flash logical sector may be mapped into supervisor or unrest...

Page 261: ...instruction address space see Figure 17 8 for details on flash sector mapping 17 3 3 7 CFMUSTAT CFM User Status Register The CFMUSTAT register defines the flash command controller status and flash me...

Page 262: ...at there are no more commands pending The CCIF flag is cleared by the flash command controller when CBEIF is cleared and sets upon completion of all active and pending commands Writing to the CCIF fla...

Page 263: ...the BLANK flag has no effect on BLANK 1 All flash memory locations or selected logical page verify as erased 0 If a blank check or page erase verify command has been executed and the CCIF flag is set...

Page 264: ...te Operation c Program erase and verify operations Section 17 4 2 3 Program Erase and Verify Operations d Stop mode Section 17 4 2 4 Stop Mode 2 Flash security operation Section 17 4 3 Flash Security...

Page 265: ...m the internal flash bus clock via a programmable counter The command register as well as the associated address and data registers operate as a buffer and a register 2 stage FIFO so that a new comman...

Page 266: ...can be executed if the CFMCLKD register has not been written to Section 17 4 2 3 5 Flash Normal Mode Illegal Operations 17 4 2 3 2 Command Write Sequence The flash command controller is used to super...

Page 267: ...check command is shown in Figure 17 14 The blank check command write sequence is as follows 1 Write to any flash memory address to start the command write sequence for the blank check command The spe...

Page 268: ...Register CFMUSTAT yes no Clear bit CBEIF 0x80 Clock Register Written Check 1 2 3 yes no Access Error and Protection Violation no and Data Bit Polling for Command Completion Check Read Register CFMUST...

Page 269: ...egister 3 Clear the CBEIF flag by writing a 1 to CBEIF to launch the page erase verify command Because the word addresses in even and odd flash blocks are interleaved pages from adjacent interleaving...

Page 270: ...gister Written Check 1 2 3 Clear bit ACCERR PVIOL 0x30 Write Register CFMUSTAT yes no Access Error and Protection Violation no and Dummy Data Bit Polling for Command Completion Check Read Register CFM...

Page 271: ...ogram flash physical blocks may be programmed simultaneously by writing to the relative address in flash physical block order even block odd block The flash physical block written to in the first arra...

Page 272: ...Bit yes Clock Register Written Check 1 2 3 no Protection Violation Check Read Register CFMUSTAT CCIF Set Bit no no Address Data Command Buffer Empty Check Next Write yes no Data Clear bit PVIOL 0x20...

Page 273: ...he flash logical page to erase while the data written during the page erase command write sequence is ignored 2 Write the page erase command 40 to the CFMCMD register 3 Clear the CBEIF flag by writing...

Page 274: ...Clock Register Written Check 1 2 3 no Protection Violation Check Read Register CFMUSTAT CCIF Set Bit no no Address Data Command Buffer Empty Check Next Write yes no and Dummy Data Clear bit PVIOL 0x20...

Page 275: ...dress and data written during the mass erase command write sequence is ignored 2 Write the mass erase command 41 to the CFMCMD register 3 Clear the CBEIF flag by writing a 1 to CBEIF to launch the mas...

Page 276: ...Violation Check Read Register CFMUSTAT CCIF Set Bit no no Address Data Command Buffer Empty Check Next Write yes no Dummy Data Clear bit PVIOL 0x20 Write Register CFMUSTAT yes PVIOL Set Bit Bit Pollin...

Page 277: ...BEIF flag after writing to the flash memory or after writing a command to the CFMCMD register but before the command is launched The PVIOL flag is set during the command write sequence if any of the f...

Page 278: ...o 32 bit writes to address 0x0400 and 0x0404 in that order The two backdoor write cycles can be separated by any number of internal flash bus cycles NOTE Any attempt to use a key of all zeros or all o...

Page 279: ...mory is erased After the next reset sequence the security state of the CFM is determined by the flash security word at address offset 0x0414 For further details on security see the MCU security specif...

Page 280: ...ColdFire Flash Module CFM MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 17 32 Freescale Semiconductor Preliminary...

Page 281: ...be programmed like standard SPI flash memories available from ST Microelectronics Macronix Spansion and other vendors The EzPort implements the same command set as devices from these vendors so exist...

Page 282: ...3 2 1 EZPCK EzPort Clock EzPort clock EZPCK is the serial clock for data transfers Serial data in EZPD and chip select EZPCS are registered on the rising edge of EZPCK while serial data out EZPQ is d...

Page 283: ...transfers It is registered on the rising edge of EZPCK All commands addresses and data are shifted in most significant bit first When EzPort is driving output data on EZPQ the data shifted in EZPD is...

Page 284: ...IPSBAR Offset Access read write 7 6 5 4 3 2 1 0 R FS WEF CRL WEN WIP W Reset 0 11 1 Reset value reflects if flash security is enabled or disabled out of reset 0 0 0 0 0 0 0 Figure 18 2 EzPort Status R...

Page 285: ...iguration register has not been loaded erase and program commands are not accepted 1 Configuration register has been loaded erase and program commands are accepted 4 2 Reserved should be cleared 1 WEN...

Page 286: ...nd is not accepted if flash security is enabled 18 4 1 7 Page Program The Page Program command programs locations in flash memory that have previously been erased The starting address of the memory to...

Page 287: ...used if the write error flag is set a write is in progress the write enable bit is not set or the configuration register has not been written 18 4 1 10 Reset Chip The Reset Chip command forces the chi...

Page 288: ...n register 1 If fSYS is greater than 25 6 MHz PRDIV8 1 otherwise PRDIV8 0 2 Determine DIV 5 0 by using the following equation Keep only the integer portion of the result and discard any fraction Do no...

Page 289: ...value written in the modulus register or it can be a free running down counter 19 1 2 Block Diagram Figure 19 1 PIT Block Diagram 19 1 3 Low Power Mode Operation This subsection describes the operati...

Page 290: ...e PIT continues to operate in its pre debug mode state but any updates made in debug mode remain 19 2 Memory Map Register Definition This section contains a memory map see Table 19 2 and describes the...

Page 291: ...read write prescaler bits select the internal bus clock divisor to generate the PIT clock To accurately predict the timing of the next count change the PRE 3 0 bits only when the enable bit EN is cle...

Page 292: ...bit from 0 to 1 during debug mode stops the PIT timer 4 OVW Overwrite Enables writing to PMRn to immediately overwrite the value in the PIT counter 0 Value in PMRn replaces value in PIT counter when...

Page 293: ...the PCSRn PIE bit is set the PIF flag issues an interrupt request to the CPU When the PCSRn OVW bit is set the counter can be directly initialized by writing to PMRn without having to wait for the cou...

Page 294: ...he CPU When the PCSRn OVW bit is set counter can be directly initialized by writing to PMRn without having to wait for the count to reach 0x0000 Figure 19 6 Counter in Free Running Mode 19 3 3 Timeout...

Page 295: ...grated Microcontroller Reference Manual Rev 1 Freescale Semiconductor 19 7 Preliminary The PIF flag is set when the PIT counter reaches 0x0000 The PIE bit enables the PIF flag to generate interrupt re...

Page 296: ...Programmable Interrupt Timers PIT0 PIT1 MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 19 8 Freescale Semiconductor Preliminary...

Page 297: ...compare which can generate output waveforms and timer software delays These functions allow simultaneous input waveform measurements and output waveform generation Additionally channel 3 can be confi...

Page 298: ...atch 16 Bit Counter Interrupt Logic TOF TOI C0F C1F Edge Detect PT1 LOGIC Edge Detect CxF Channel 2 Channel3 GPTC3H GPTC3L 16 Bit Comparator 16 Bit Latch C3F PT3 LOGIC Edge Detect IOS0 IOS1 IOS3 OM OL...

Page 299: ...the signal properties 20 5 1 GPT 2 0 The GPT 2 0 pins are for channel 2 0 input capture and output compare functions These pins are available for general purpose input output I O when not configured f...

Page 300: ...a Register GPTOC3D 8 R W 0x00 20 6 4 20 7 0x1A_0004 GPT Counter Register High GPTCNTH 2 8 R 0x00 20 6 5 20 7 0x1A_0005 GPT Counter Register Low GPTCNTL 2 8 R 0x00 20 6 5 20 7 0x1A_0006 GPT System Cont...

Page 301: ...16 0x1A_001E GPT Port Data Direction Register GPTDDR 8 R W 0x00 20 6 19 20 16 1 Addresses not assigned to a register and undefined register bits are reserved for expansion 2 This register is 16 bits w...

Page 302: ...ss Supervisor read write 7 6 5 4 3 2 1 0 R 0 0 0 0 FOC W Reset 0 0 0 0 0 0 0 0 Figure 20 3 GPT Input Compare Force Register GPCFORC Table 20 5 GPTCFORC Field Descriptions Field Description 7 4 Reserve...

Page 303: ...hen the pin is configured for output compare IOSx 1 The OC3Mn bits do not change the state of the PORTTnDDR bits These bits are read anytime write anytime 1 Corresponding PORTTn pin configured as outp...

Page 304: ...rite 7 6 5 4 3 2 1 0 R GPTEN 0 TFFCA 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 20 7 GPT System Control Register 1 GPTSCR1 Table 20 9 GPTSCR1 Field Descriptions Field Description 7 GPTEN Enables the gener...

Page 305: ...4 Reserved should be cleared 3 0 TOV Toggles the output compare pin on overflow for each channel This feature only takes effect when in output compare mode When set it takes precedence over forced out...

Page 306: ...ote Channel 3 shares a pin with the pulse accumulator input pin To use the PAI input clear the OM3 and OL3 bits and clear the OC3M3 bit in the output compare 3 mask register IPSBAR Offset 0x1A_000B GP...

Page 307: ...ystem Control Register 2 GPTSCR2 Table 20 14 GPTSCR2 Field Descriptions Field Description 7 TOI Enables timer overflow interrupt requests 1 Overflow interrupt requests enabled 0 Overflow interrupt req...

Page 308: ...LG1 Access Supervisor read write 7 6 5 4 3 2 1 0 R 0 0 0 0 CF W Reset 0 0 0 0 0 0 0 0 Figure 20 14 GPT Flag Register 1 GPTFLG1 Table 20 15 GPTFLG1 Field Descriptions Field Description 7 4 Reserved sho...

Page 309: ...ed should be cleared IPSBAR Offsets 0x1A_0010 GPTC0 0x1A_0012 GPTC1 0x1A_0014 GPTC2 0x1A_0016 GPTC3 Access Supervisor read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CCNT W Reset 0 0 0 0 0 0 0 0 0...

Page 310: ...PAI input enables divide by 64 clock to pulse accumulator and trailing falling edge on PAI sets PAIF flag Note The timer prescaler generates the divide by 64 clock If the timer is not active there is...

Page 311: ...detected at the PAI pin In event counter mode the event edge sets PAIF In gated time accumulation mode the trailing edge of the gate signal at the PAI pin sets PAIF If the PAI bit in GPTPACTL is also...

Page 312: ...s buffered and drives the pins only when they are configured as general purpose outputs Reading an input DDR bit 0 reads the pin state reading an output DDR bit 1 reads the latched value Writing to a...

Page 313: ...PT counter reaches the value in the channel registers of an output compare channel the timer can set clear or toggle the channel pin An output compare on channel n sets the CnF flag The CnI bit enable...

Page 314: ...output logic by clearing the channel 3 output mode and output level bits OM3 and OL3 Also clear the channel 3 output compare 3 mask bit OC3M3 The PA counter register GPTPACNT reflects the number of a...

Page 315: ...RTTn pins as input capture or output compare pins The PORTTn data direction register controls the data direction of an input capture pin External pin conditions trigger input captures on input capture...

Page 316: ...l output GPT disabled by GPTEN 0 1 0 0 IC 0 IC disabled X 0 In Ext Digital input Input capture disabled by EDGn setting 1 1 0 0 X 0 Out Data reg Digital output Input capture disabled by EDGn setting 1...

Page 317: ...n the 16 bit pulse accumulator rolls over from 0xFFFF to 0x0000 If the PAOVI bit in GPTPACTL is also set PAOVF generates an interrupt request Clear PAOVF by writing a 1 to this flag NOTE When the fast...

Page 318: ...flag NOTE When the fast flag clear all enable bit GPTSCR1 TFFCA is set any access to the pulse accumulator counter registers clears all the flags in GPTPAFLG 20 9 4 Timer Overflow TOF TOF is set when...

Page 319: ...imer modules DTIM0 DTIM1 DTIM2 or DTIM3 21 1 1 Overview Each DMA timer module has a separate register set for configuration and control The timers can be configured to operate from the internal bus cl...

Page 320: ...e interrupt or DMA request on input capture or reference compare Ability to stop the timer from counting when the ColdFire core is halted 21 2 Memory Map Register Definition The timer module registers...

Page 321: ...0x00_04C2 DMA Timer n Extended Mode Register DTXMRn 8 R W 0x00 21 2 2 21 4 0x00_0403 0x00_0443 0x00_0483 0x00_04C3 DMA Timer n Event Register DTERn 8 R W 0x00 21 2 3 21 5 0x00_0404 0x00_0444 0x00_0484...

Page 322: ...ls 0 0 Disable DMA request or interrupt for reference reached does not affect DMA request or interrupt on capture function 1 Enable DMA request or interrupt upon reaching the reference value 3 FRR Fre...

Page 323: ...s Field Description 7 DMAEN DMA request Enables DMA request output on counter reference match or capture edge event 0 DMA request disabled 1 DMA request enabled 6 HALTED Controls the counter when the...

Page 324: ...Output reference event The counter value DTCNn equals the reference value DTRRn Writing a 1 to REF clears the event condition Writing a 0 has no effect 0 CAP Capture event The counter value has been...

Page 325: ...d by 16 or DTINn IPSBAR Offset 0x00_0404 DTRR0 0x00_0444 DTRR1 0x00_0484 DTRR2 0x00_04C4 DTRR3 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 326: ...n DMAEN are set a DMA request is asserted If DTERn CAP is set and DTXMRn DMAEN is cleared an interrupt is asserted 21 3 3 Reference Compare Each DMA timer can be configured to count up to a reference...

Page 327: ...source when the timer capture mode is selected or indeterminate operation results The 8 bit DTMRn PS prescaler value is set Using DTMRn RST counter is cleared and started Timer events are managed wit...

Page 328: ...o the register setting TMR0 RST T0_LOOP move b TER0 D1 load TER0 and see if btst 1 D1 TER0 REF has been set beq T0_LOOP addi l 1 D2 Increment D2 cmp l 5 D2 Did D2 reach 5 i e timer ref has timed beq T...

Page 329: ...al RAM organization The chapter concludes with the programming model and a timing diagram 22 1 1 Block Diagram Figure 22 1 illustrates the QSPI module Figure 22 1 QSPI Block Diagram Queue Control Bloc...

Page 330: ...e for details on which chip selects are pinned out Baud rates from 129 4 Kbps to 16 6 Mbps at 66 MHz internal bus frequency Programmable delays before and after transfers Programmable QSPI clock phase...

Page 331: ...ns Signal Name Hi Z or Actively Driven Function QSPI Data Output QSPI_DOUT Configurable Serial data output from QSPI QSPI Data Input QSPI_DIN N A Serial data input to QSPI Serial Clock QSPI_CLK Active...

Page 332: ...CPOL Clock polarity Defines the clock polarity of QSPI_CLK 0 The inactive state value of QSPI_CLK is logic level 0 1 The inactive state value of QSPI_CLK is logic level 1 8 CPHA Clock phase Defines t...

Page 333: ...tes transfers in master mode by executing commands in the command RAM Automatically cleared by the QSPI when a transfer completes The user can also clear this bit to abort transfer unless QIR ABRTL is...

Page 334: ...NEWQP and continue execution 13 WRTO Wraparound location Determines where the QSPI wraps to in wraparound mode 0 Wrap to RAM entry zero 1 Wrap to RAM entry pointed to by QWR NEWQP 12 CSIV QSPI_CS inac...

Page 335: ...sults in an access error 13 Reserved should be cleared 12 ABRTL Abort lock out When set QDLYR SPE cannot be cleared by writing to the QDLYR QDLYR SPE is only cleared by the QSPI when a transfer comple...

Page 336: ...d enables external peripherals for transfer The command field provides transfer operations IPSBAR Offset 0x00_0350 QAR Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0...

Page 337: ...max of 16 words Note To keep the chip selects asserted for transfers beyond 16 words the QWR CSIV bit must be set to control the level that the chip selects return to after the first transfer 14 BITSE...

Page 338: ...r QWR ENDQP points to the final command in the queue The internal pointer is initialized to the same value as QWR NEWQP During normal operation the following sequence repeats 1 The command pointed to...

Page 339: ...s are undefined immediately after a reset The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data 16 words of re...

Page 340: ...consists of 16 bytes each divided into two fields The peripheral chip select field controls the QSPI_CS signal levels for the transfer The command control field provides transfer options A maximum of...

Page 341: ...CR DSCK equals zero the standard delay of one half the QSPI_CLK period is used The command RAM delay after transmit enable bit QCR DT enables the programmable delay period from the negation of the QSP...

Page 342: ...nsmit RAM is loaded into the data serializer and transmitted Data that is simultaneously received is stored at the pointer address in receive RAM When the proper number of bits has been transferred th...

Page 343: ...of 4 125 MHz The QSPI RAM is set up for a queue of 16 transfers All four QSPI_CS signals are used in this example 1 Write the QMR with 0xB308 to set up 12 bit data words with the data shifted on the f...

Page 344: ...Queued Serial Peripheral Interface QSPI MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 22 16 Freescale Semiconductor Preliminary...

Page 345: ...each of the three independent UARTs eliminating the need for an external UART clock As Figure 23 1 shows each UART module interfaces directly to the CPU and consists of Serial communication channel P...

Page 346: ...or use DMA requests for servicing See Section 23 4 2 2 Receiver NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins refer to Chapter 13 General Purpose I...

Page 347: ...ytes NOTE Interrupt can mean an interrupt request asserted to the CPU or a DMA request Table 23 1 UART Module Signals Signal Description UTXDn Transmitter Serial Data Output UTXDn is held high mark co...

Page 348: ...FF 23 3 6 23 11 UART Transmit Buffers UTBn 8 W 0x00 23 3 7 23 12 0x00_0210 0x00_0250 0x00_0290 UART Input Port Change Register UIPCRn 8 R See Section 23 3 8 23 12 UART Auxiliary Control Register UACRn...

Page 349: ...or URTSn control URTSn control is disabled for both Transmitter RTS control is configured in UMR2n TXRTS 0 The receiver has no effect on URTSn 1 When a valid start bit is received URTSn is negated if...

Page 350: ...equals 11 1 0 B C Bits per character Selects the number of data bits per character to be sent The values shown do not include start parity or stop bits 00 5 bits 01 6 bits 10 7 bits 11 8 bits IPSBAR...

Page 351: ...nd TXRTS are set TXCTS controls the operation of the transmitter 0 UCTSn has no effect on the transmitter 1 Enables clear to send operation The transmitter checks the state of UCTSn each time it is re...

Page 352: ...y or force parity the corresponding character in the FIFO was received with incorrect parity If UMR1n PM equals 11 multidrop PE stores the received address or data A D bit PE is valid only when RXRDYe...

Page 353: ...s 1 A character was received and the receiver FIFO is now full Any characters received when the FIFO is full are lost 0 RXRDY Receiver ready 0 The CPU has read the receive buffer and no characters rem...

Page 354: ...n a known state use this command instead of RECEIVER DISABLE when reconfiguring the receiver 011 RESET TRANSMITTER Immediately disables the transmitter and clears USRn TXEMP TXRDY No other registers a...

Page 355: ...TXRDY are set If the transmitter is already enabled this command has no effect 10 TRANSMITTER DISABLE Terminates transmitter operation and clears USRn TXEMP TXRDY If a character is being sent when the...

Page 356: ...ites to the transmit buffer when the UART s TXRDY equals 0 and the transmitter is disabled have no effect on the transmit buffer Figure 23 9 shows UTBn TB contains the character in the transmit buffer...

Page 357: ...CPU last read UIPCRn Reading UIPCRn clears UISRn COS 1 A change of state longer than 25 50 s occurred on the UCTSn input UACRn can be programmed to generate an interrupt to the CPU when a change of s...

Page 358: ...eared 2 DB Delta break 0 No new break change condition to report Section 23 3 5 UART Command Registers UCRn describes the RESET BREAK CHANGE INTERRUPT command 1 The receiver detected the beginning or...

Page 359: ...he UART transmitter or receiver are enabled UBG1n and UBG2n are write only and cannot be read by the CPU 23 3 12 UART Input Port Register UIPn The UIPn registers shown in Figure 23 15 show the current...

Page 360: ...to produce standard UART baud rates Table 23 11 UIPn Field Descriptions Field Description 7 1 Reserved 0 CTS Current state of clear to send The UCTSn value is latched and reflects the state of the in...

Page 361: ...n UBG2n The choice of DTIN or internal bus clock is programmed in the UCSR Figure 23 17 Clocking Source Diagram NOTE If DTINn is a clocking source for the timer or UART that timer module cannot use DT...

Page 362: ...er to Section 23 3 Memory Map Register Definition Figure 23 18 Transmitter and Receiver Functional Diagram 23 4 2 1 Transmitter The transmitter is enabled through the UART command register UCRn When i...

Page 363: ...UCRn The transmitter is reenabled through the UCRn to resume operation after a disable or software reset If the clear to send operation is enabled UCTSn must be asserted for the character to be transm...

Page 364: ...f the bit until the proper number of data bits and parity if any is assembled and one stop bit is detected Data on the URXDn input is sampled on the rising edge of the programmed clock source The lsb...

Page 365: ...er time receiver places an all zero character into the Rx FIFO and sets USRn RB RXRDY Figure 23 20 shows receiver functional timing Figure 23 20 Receiver Timing Diagram 23 4 2 3 FIFO The FIFO is used...

Page 366: ...FIFO The FIFO is popped only when the receive buffer is read The USRn should be read before reading the receive buffer If all three receiver holding registers are full a new character is held in the r...

Page 367: ...the operation of a UART by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations Figure 23 22 Local Loopback Features of this local loopback mode are...

Page 368: ...n the master sends an address character the slave receiver notifies its respective CPU by setting USRn RXRDY and generating an interrupt if programmed to do so Each slave station CPU then compares the...

Page 369: ...discarded if the received A D bit is 0 data tag If the receiver is enabled all received characters are transferred to the CPU through the receiver holding register during read operations In either ca...

Page 370: ...n called SINIT places the UART in local loopback mode and checks for the following errors Transmitter never ready Receiver never ready Parity error Incorrect character received I O driver routine This...

Page 371: ...the UART programming model to determine the end of transmission status Similarly the receive DMA request signal is asserted when the FIFO full or receive ready FFULL RXRDY flag in the interrupt status...

Page 372: ...the GPACR and appropriate PACR registers located in the SCM for DMA access to IPSBAR space 4 Initialize the DMA channel The DMA should be configured for cycle steal mode and a source and destination s...

Page 373: ...ready to send TXRTS c If preferred program operation of clear to send TXCTS bit d Select stop bit length SB bits 7 UCRn Enable transmitter and or receiver Figure 23 25 UART Mode Programming Flowchart...

Page 374: ...Mode Programming Flowchart Sheet 2 of 5 CHCHK CHCHK Place Channel In Local Loopback Mode Enable Transmitter Clear Status Word TxCHK Is Transmitter Ready Y N SNDCHR RxCHK Send Character To Transmitter...

Page 375: ...Figure 23 25 UART Mode Programming Flowchart Sheet 3 of 5 A B B FRCHK Have Framing Error Set Framing Error Flag PRCHK Have Parity Error Set Parity Error Flag Get Character From Receiver Same As Trans...

Page 376: ...4 of 5 Was IRQ Caused By Beginning Of A Break SIRQ ABRKI N Clear Change in Break Status Bit ABRKI1 N Has End of break IRQ Arrived Yet Y Y Clear Change in Break Status Bit Remove Break Character From...

Page 377: ...ldFire Integrated Microcontroller Reference Manual Rev 1 Freescale Semiconductor 23 33 Preliminary Figure 23 25 UART Mode Programming Flowchart Sheet 5 of 5 OUTCH Is Transmitter Ready N Y Send Charact...

Page 378: ...UART Modules MCF52110 ColdFire Integrated Microcontroller Reference Manual Rev 1 23 34 Freescale Semiconductor Preliminary...

Page 379: ...ion This chapter describes the I2 C module clock synchronization and I2 C programming model registers It also provides extensive programming examples NOTE The MCF52110 contains two I2 C modules I2 C0...

Page 380: ...two wire bidirectional serial bus that provides a simple efficient method of data exchange minimizing the interconnection between devices This bus is suitable for applications that require occasional...

Page 381: ...NOTE The I2 C module is compatible with the Philips I2 C bus protocol For information on system configuration protocol and restrictions see The I2 C Bus Specification Version 2 1 NOTE The GPIO module...

Page 382: ...gister Access Reset Value Section Page I2 C0 I2C1 0x0300 0x0380 I2 C Address Registers I2ADRn R W 0x00 24 2 1 24 4 0x0304 0x0384 I2 C Frequency Divider Registers I2FDRn R W 0x00 24 2 2 24 4 0x0308 0x0...

Page 383: ...k frequency is equal to the internal bus clock divided by the divider shown below Due to potentially slow SCL and SDA rise and fall times bus signals are sampled at the prescaler frequency IC Divider...

Page 384: ...not cleared 1 I2 C module interrupts are enabled An I2 C interrupt occurs if I2SR IIF is also set 5 MSTA Master slave mode select bit If the master loses arbitration MSTA is cleared without generatin...

Page 385: ...t SDA sampled low when the master drives high during an address or data transmit cycle SDA sampled low when the master drives high during the acknowledge bit of a data receive cycle A start cycle is a...

Page 386: ...ing a START signal see A in Figure 24 7 A START signal is defined as a high to low transition of SDA while SCL is high This signal denotes the beginning of a data transfer each data transfer can be se...

Page 387: ...24 7 on a byte by byte basis in the direction specified by the R W bit sent by the calling master Data can be changed only while SCL is low and must be held stable while SCL is high as Figure 24 7 sh...

Page 388: ...o the slave The slave releases SDA for the master to generate a STOP or START signal Figure 24 9 24 3 5 STOP Signal The master can terminate communication by generating a STOP signal to free the bus A...

Page 389: ...is to communicate with same slave in a different mode without releasing the bus The master transmits data to the slave first and then the master reads data from slave by reversing the R W bit Figure...

Page 390: ...st low period Devices with shorter low periods enter a high wait state during this time see Figure 24 12 When all devices concerned have counted off their low period the synchronized clock SCL line is...

Page 391: ...ock See Section 24 2 2 I2C Frequency Divider Registers I2FDRn 2 Update the I2ADR to define its slave address 3 Set I2CR IEN to enable the I2 C bus interface system 4 Modify the I2CR to select or desel...

Page 392: ...nitoring the IIF bit if the interrupt function is disabled Polling should monitor IIF rather than ICF because that operation is different when arbitration is lost When an interrupt occurs at the end o...

Page 393: ...matically The only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred interrupts resulting from subsequent data transfers have IAAS cleared...

Page 394: ...R Switch to Rx Mode Dummy Read from I2DR Generate STOP Signal Read Data from I2DR And Store Set TXAK 1 Generate STOP Signal 2nd Last Byte to be Last Byte to be Arbitration Lost Clear IAL IAAS 1 IAAS 1...

Page 395: ...5 3 s using simultaneous mode Ability to simultaneously sample and hold 2 inputs Ability to sequentially scan and store up to 8 measurements Internal multiplex to select two of 8 inputs Power savings...

Page 396: ...ntrol Register 1 CTRL1 16 R W 0x5005 25 4 1 25 3 0x19_0002 Control Register 2 CTRL2 16 R W 0x0002 25 4 2 25 5 0x19_0004 Zero Crossing Control Register ADZCC 16 R W 0x0000 25 4 3 25 8 0x19_0006 Channel...

Page 397: ...t 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 Figure 25 2 Control 1 Register CTRL1 Table 25 2 CTRL1 Field Descriptions Field Description 15 Reserved should be cleared 14 STOP0 Stop Conversion 0 bit When STOP0 is...

Page 398: ...EOSI0 interrupt to be generated upon completion of the scan For looping scan modes the interrupt triggers after the completion of each iteration of the loop 0 Interrupt disabled 1 Interrupt enabled 1...

Page 399: ...Loop sequential 011 Loop parallel 100 Triggered sequential 101 Triggered parallel default 110 Reserved do not use 111 Reserved do not use IPSBAR Offset 0x19_0002 CTRL2 Access read write 15 14 13 12 1...

Page 400: ...the value of DIV for several configurations IPSBAR Offset 0x19_0002 CTRL2 Access read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 STOP1 SYNC1 EOSIE1 0 0 0 0 0 SIMU LT DIV W START1 Reset 0 1 0 1 0...

Page 401: ...the SYNC0 input are used to start and stop scans in both converters simultaneously A scan ends in both converters when either converter encounters a disabled sample slot When the parallel scan complet...

Page 402: ...tial modes the sample slots are converted in order from SAMPLE0 to SAMPLE7 Analog input pins can be sampled in any order including sampling the same input pin more than once In parallel modes converte...

Page 403: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SAMPLE3 SAMPLE2 SAMPLE1 SAMPLE0 W Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Figure 25 6 Channel List 1 Register ADLST1 Table 25 7 ADLST1 Field Descriptions Field Descr...

Page 404: ...Reserved should be cleared 14 12 SAMPLE7 Sample input channel select 7 The settings for this field are given in Table 25 9 11 Reserved should be cleared 10 8 SAMPLE6 Sample input channel select 6 The...

Page 405: ...cleared They are not cleared automatically on the next scan sequence IPSBAR Offset 0x19_000A ADSDIS Access read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 DS7 DS6 DS5 DS4 DS3 DS2 DS...

Page 406: ...mpleted end of scan IRQ pending 11 EOSI0 End of Scan Interrupt 0 bit This bit indicates whether a scan of analog inputs has been completed since the last read of ADSTAT or a reset The EOSI0 bit is cle...

Page 407: ...a read from the corresponding ADC results ADRSLTn register If polling the RDYn bits to determine if a particular sample is executed care should be taken not to start a new scan until all enabled samp...

Page 408: ...portion of the value written is used This value is modified as shown in Figure 25 23 and the result of the subtraction is stored The SEXT bit is only set as a result of this subtraction and is not di...

Page 409: ...and ADHLMTn correspond to result registers ADRSLTn The high limit register is used for the comparison of result high limit The low limit register is used for the comparison of result low limit Limit...

Page 410: ...5 13 Low Limit Registers ADLLMTn Table 25 15 ADLLMTn Field Descriptions Field Description 15 Reserved should be cleared 14 3 LLMT Low limit 2 0 Reserved should be cleared IPSBAR Offset 0x19_0032 ADHLM...

Page 411: ...re undefined The voltage reference generator and at least one converter must be powered up to use the ADC module 2 Manual power down controls Each converter and the voltage reference generator have a...

Page 412: ...write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ASB 0 0 PSTS2 PSTS1 PSTS0 PUDELAY APD PD2 PD1 PD0 W Reset 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 Figure 25 16 Power Control Register POWER Table 25 18 POWER Fie...

Page 413: ...ease refer to the Device Data Sheet for further details 3 APD Auto Power Down Mode bit Auto power down mode disables converters when they are not in use for a scan APD takes precedence over ASB When a...

Page 414: ...for Converter A bit This bit forces Converter A to power down Setting PD0 powers down converter A immediately The results of a scan using converter A is invalid when PD0 is set When PD0 is cleared co...

Page 415: ...converter A and in order SAMPLE4 7 by converter B in parallel scan SAMPLE slots may be disabled using the SDIS register The following pairs of analog inputs can be configured as a differential pair A...

Page 416: ...in its part of SDIS register DS0 DS3 for A DS4 DS7 for B Figure 25 19 Parallel Mode Operation of the ADC The ADC can be configured to perform a single scan and halt perform a scan when triggered or p...

Page 417: ...an be directed to ADRSLT0 3 and any of AN4 AN7 can be directed to ADRSLT4 7 4 MUXing for parallel mode differential conversions During any conversion cycle sample either member of differential pair AN...

Page 418: ...and the middle switch is closed providing the differential channel to the differential input of the A D Table 25 20 Analog MUX Controls for Each Conversion Mode continued Conversion Mode Channel Selec...

Page 419: ...irects it to the plus terminal of the A D core The minus terminal of the A D core is connected to the VREFL reference during this mode The ADC measures the voltage of the selected analog input and com...

Page 420: ...return the max value 32760 4095 8 when the plus input is VREFH and the minus input is VREFL return 0 when the plus input is at VREFL and the minus input is at VREFL and scale linearly between based o...

Page 421: ...lue is unsigned and equals the cyclic converter unsigned result The range of the result registers ADRSLTn is 0x0000 0x7FF8 assuming the offset ADOFSn registers are set to zero The processor can write...

Page 422: ...r by CHNCFG A differential measurement is made if a SAMPLE slot refers to either member of a differential pair Refer to the CHNCFG field description in the CTRL1 register for details of differential a...

Page 423: ...ns in the A and B converter start and stop independently according to their own controls They may be simultaneous phase shifted or asynchronous depending on when scans are initiated on the respective...

Page 424: ...of the 8 sample slots defined by the ADLST1 and ADLST2 registers A scan is the process of stepping through these sample slots converting the analog input indicated by that slot and storing the result...

Page 425: ...ied only on the first conversion Loop parallel Upon an initial start or enabled sync pulse converter A captures Samples 0 3 and converter B captures Samples 4 7 Each time a converter completes its cur...

Page 426: ...DC s clock is enabled ADC 1 in the SIM module s SIM_PCE register In this mode the ADC uses the conversion clock as the ADC clock source when active or idle To minimize conversion latency it is recomme...

Page 427: ...xecuted at the start of all scans allowing the ADC to stabilize when switching to normal current mode from a completely powered off condition This mode uses less power than normal and more power than...

Page 428: ...powered at the start of the scan In auto power down mode when the ADC goes from idle to active a converter is only powered up if it is required for the scan as determined by the ADLST1 ADLST2 and SDI...

Page 429: ...if power management is set to normal It is also active during all ADC power up for a period of time determined by the PUDELAY field in the power POWER register After the power up delay times out the A...

Page 430: ...and SYNCn signals As shown in Figure 25 27 the first scan started is re synchronized to the system clock but the second scan may wait up to 5 additional system clocks before starting Also which conver...

Page 431: ...rence current Figure 25 28 ADC Voltage Reference Circuit When tying VREFH to the same potential as VDDA relative measurements are being made with respect to the amplitude of VDDA It is imperative that...

Page 432: ...ult Figure 25 28 illustrates the internal workings of the ADC voltage reference circuit VREFH must be noise filtered a minimum configuration is shown in the figure 25 5 11 Supply Pins VDDA and VSSA De...

Page 433: ...onous series of pulses having programmable period and duty cycle With a suitable low pass filter the PWM can be used as a digital to analog converter Figure 26 1 PWM Block Diagram Internal Bus Clock f...

Page 434: ...fined register bits are reserved for expansion Write accesses to these reserved address spaces and reserved register bits have no effect 2 A 32 bit access to any of these registers results in a bus tr...

Page 435: ...e at PWMOUT6 when its corresponding clock source begins its next cycle If PWMCTL CON67 is set then this bit has no effect and PWMOUT6 is disabled 0 PWM output disabled 1 PWM output enabled 5 PWME5 PWM...

Page 436: ...PWMOUT1 when its corresponding clock source begins its next cycle 0 PWM output disabled 1 PWM output enabled 0 PWME0 PWM Channel 0 Output Enable If enabled the PWM signal becomes available at PWMOUT0...

Page 437: ...MCLK Field Descriptions Field Description 7 0 PCLKn PWM channel n clock select Selects between one of two clock sources for each PWM channel See Section 26 2 4 PWM Prescale Clock Select Register PWMPR...

Page 438: ...26 5 PWMPRCLK Field Descriptions Field Description 7 Reserved should be cleared 6 4 PCKB Clock B prescaler select These three bits control the rate of Clock B which can be used for PWM channels2 3 6...

Page 439: ...rder byte and channel 6 the low order byte PWMOUT7 is the output for this 16 bit PWM signal and PWMOUT6 is disabled The channel 7 clock select polarity center align enable and enable bits control this...

Page 440: ...oze mode 1 Stop the input clock to the prescaler when the core is in doze mode 2 PFRZ PWM counters stop in debug mode BKPT asserted 0 Allow PWM counters to continue while in debug mode 1 Disable PWM i...

Page 441: ...gned output mode the counter counts from 0 up to the value in the period register and then back down to 0 Therefore given the same value in the period register center aligned mode is twice the period...

Page 442: ...and Duty for more information Calculating the output period depends on the output mode center aligned has twice the period as left aligned mode as well as PWMPERn See the below equation Eqn 26 3 For b...

Page 443: ...0017 PWMPER3 0x1B_0018 PWMPER4 0x1B_0019 PWMPER5 0x1B_001A PWMPER6 0x1B_001B PWMPER7 Access User Read Write 7 6 5 4 3 2 1 0 R PERIOD W Reset 1 1 1 1 1 1 1 1 Figure 26 11 PWM Period Registers PWMPERn T...

Page 444: ...tdown Register PWMSDN Table 26 13 PWMSDN Field Descriptions Field Description 7 IF PWM interrupt flag Any change in state of PWM7IN is flagged by setting this bit The flag is cleared by writing a 1 to...

Page 445: ...ammable to run at clock A and B divided by 2 4 or 512 Each PWM channel has the capability of selecting one of two clocks the prescaled clock clock A or B or the scaled clock clock SA or SB The block d...

Page 446: ...PWM The input clock is also disabled when all PWM channels are disabled PWMEn 0 Clock A and B are scaled values of the input clock The value is software selectable for clock A and B and has options of...

Page 447: ...8 bit down counter to be re loaded Otherwise when changing rates the counter would have to count down to 0x01 before counting at the proper rate Forcing the associated counter to re load the scale reg...

Page 448: ...elect When one of the bits in the PWMPOL register is set the associated PWM channel output is high at the beginning of the waveform then goes low when the duty count is reached Conversely if the polar...

Page 449: ...tion to be set to up the immediate load of duty and period registers with values from the buffers and the output to change according to the polarity bit When the channel is disabled PWMEn 0 the counte...

Page 450: ...igure 26 3 2 3 The counter counts from 0 to the value in the period register minus 1 NOTE Changing the PWM output mode from left aligned to center aligned output or vice versa while channels are opera...

Page 451: ...put to also change state When the PWM counter decrements and reaches zero the counter direction changes from a down count back to an up count and a load from the double buffer period and duty register...

Page 452: ...disabled As shown in Figure 26 20 when channels 2 and 3 are concatenated channel 2 registers become the high order bytes of the double byte channel When channels 0 and 1 are concatenated channel 0 reg...

Page 453: ...s The following table summarizes the boundary conditions for the PWM regardless of the output mode left or center aligned and 8 bit normal or 16 bit concatenation Table 26 15 16 bit Concatenation Mode...

Page 454: ...r Preliminary Table 26 16 PWM Boundary Cases PWMDTYn PWMPERn PPOLn PWMn Output 0x00 indicates no duty 0x00 1 Always Low 0x00 indicates no duty 0x00 0 Always High XX 0x001 indicates no period 1 Counter...

Page 455: ...essor complex In BDM processor complex is halted and a variety of commands can be sent to the processor to access memory registers and peripherals The external emulator uses a three pin serial full du...

Page 456: ...does not affect hardware breakpoint logic Added BDM address attribute register BAAR BKPT configurable interrupt CSR BKD Level 1 and level 2 triggers on OR condition in addition to AND SYNC_PC command...

Page 457: ...Its rising edge appears in the center of valid PST and DDATA output PSTCLK indicates when the development system should sample PST and DDATA values The following figure shows PSTCLK timing with respec...

Page 458: ...ed For some opcodes a branch target address may be displayed on DDATA depending on the CSR settings CSR also controls the number of address bytes displayed indicated by the PST marker value preceding...

Page 459: ...processor clock cycles 1 Use PST 0x5 to identify that a taken branch is executed 2 Using the PST pins optionally signal the target address to be displayed sequentially on the DDATA pins Encodings 0x9...

Page 460: ...are treated as 32 bit quantities regardless of the number of implemented bits These registers are also accessed through the BDM port by the commands WDMREG and RDMREG described in Section 27 5 3 3 Co...

Page 461: ...to the shared function For example if an operand address breakpoint is loaded into the debug module a BDM command to access memory overwrites an address breakpoint in ABHR If a data breakpoint is conf...

Page 462: ...Hardware Breakpoint Trigger If TRG is set a hardware breakpoint halted the processor core and forced entry into BDM Reset the debug GO command or reading CSR from the BDM port only clear TRG 25 HALT P...

Page 463: ...get address See Section 27 3 1 Begin Execution of Taken Branch PST 0x5 7 Reserved must be cleared 6 NPL Non Pipelined Mode Determines whether the core operates in pipelined mode or not 0 Pipelined mod...

Page 464: ...he trigger The register value is compared with address attribute signals from the processor s local high speed bus as defined by the setting of the trigger definition register TDR AATR is accessible i...

Page 465: ...riptions Field Description 15 RM Read write Mask Setting RM masks R in address comparisons 14 13 SZM Size Mask Setting an SZM bit masks the corresponding SZ bit in address comparisons 12 11 TTM Transf...

Page 466: ...ommand 4 3 TT Transfer Type Compared with the local bus transfer type signals 00 Normal processor access 01 Reserved 10 Emulator mode access 11 Acknowledge CPU space access These bits also define the...

Page 467: ...ed 29 L2EBL Enable Level 2 Breakpoint Global enable for the breakpoint trigger 0 Disables all level 2 breakpoints 1 Enables all level 2 breakpoint triggers 28 22 L2ED Enable Level 2 Data Breakpoint Se...

Page 468: ..._condition Address_range Data_condition 1 Level 2 trigger PC_condition Address_range Data_condition Note Debug Rev A only had the AND condition available for the triggers 14 L1T Level 1 Trigger Determ...

Page 469: ...f a data value other than the DBR contents 0 No inversion 1 Invert data breakpoint comparators 4 2 L1EA Enable Level 1 Address Breakpoint Setting an L1EA bit enables the corresponding address breakpoi...

Page 470: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Address Reset Figure 27 7 PC Breakpoint Register PBR0 Table 27 10 PBR0 Field Descriptions Field Description 31...

Page 471: ...ly 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Mask Reset Figure 27 9 PC Breakpoint Mask Register PBMR Table 27 12 PBMR Field Descriptions Field Descripti...

Page 472: ...nly BDM write only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Data Reset Figure 27 11 Data Breakpoint Registers DBR Table 27 15 DBR Field Descriptions Fi...

Page 473: ...ful for flash programming Provides absolute control of the processor and thus the system This feature allows quick hardware debugging with the same tool set used for firmware development 27 5 1 CPU Ha...

Page 474: ...oint Specifically if the PC register was loaded the GO command causes the processor to exit halted state and pass control to the instruction address in the PC bypassing normal reset exception processi...

Page 475: ...O cannot be used to indicate the start of a serial transfer The development system must count clock cycles in a given transfer C0 C4 are described as C0 Set the state of the DSI bit C1 First synchroni...

Page 476: ...generated messages listed below The not ready response can be ignored unless a memory referencing cycle is in progress Otherwise the debug module can accept a new serial transfer after 32 processor c...

Page 477: ...yte 0x1840 word 0x1880 lword Dump memory block DUMP Used with READ to dump large blocks of memory An initial READ executes to set up the starting address of the block and to retrieve the first result...

Page 478: ...address data or operand data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operation 0 R W Op Size 0 0 A D Register Extension Word s Figure 27 16 BDM Command Format Table 27 21 BDM Field Descriptions Field De...

Page 479: ...by the illegal command encoding If this occurs the development system should retransmit the command NOTE A not ready response can be ignored except during a memory referencing cycle Otherwise the deb...

Page 480: ...lly completed commands S equals 1 for illegal commands not ready responses and transfers with bus errors Section 27 5 2 BDM Serial Interface describes the receive packet format Freescale reserves unas...

Page 481: ...s or data register The data is supplied most significant word first Result Data Command complete status is indicated by returning 0xFFFF with S cleared when the register write is complete 27 5 3 3 3 R...

Page 482: ...e is undefined 0x0001 S equals 1 is returned if a bus error occurs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0x1 0x9 0x0 0x0 A 31 16 A 15 0 Result X X X X X X X X D 7 0 Word Command 0x1 0x9 0...

Page 483: ...TM defines address space Hardware forces low order address bits to 0s for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned Command...

Page 484: ...READ command to access large blocks of memory An initial READ is executed to set up the starting address of the block and to retrieve the first result If an initial READ is not executed before the fir...

Page 485: ...allowing the operand size to be dynamically altered Command Result Formats Command Sequence Figure 27 27 DUMP Command Sequence Operand Data None 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0x1...

Page 486: ...d saves in a temporary register after the memory write Subsequent FILL commands use this address perform the write increment it by the current operand size and store the updated address in the tempora...

Page 487: ...efore normal instruction execution resumes Prefetching begins at the current address in the PC and at the current privilege level If any register such as the PC or SR is altered by a BDM command while...

Page 488: ...ayed The processor then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of the CSR BTB bits The specific sequence of PST and DDATA values is...

Page 489: ...essor memory control registers are always 32 bits wide regardless of register width The second and third words of the command form a 32 bit address which the debug module uses to generate a special bu...

Page 490: ...ot uniquely identify one as the SSP and the other as the USP Rather the hardware uses one 32 bit register as the currently active A7 the other is named the OTHER_A7 Therefore the contents of the two h...

Page 491: ...description for the Rc encoding and for additional notes on writes to the A7 stack pointers and the EMAC programming model Command Result Formats Command Sequence Figure 27 39 WCREG Command Sequence O...

Page 492: ...mand Sequence Operand Data None Result Data The contents of the selected debug register are returned as a longword value The data is returned most significant word first 27 5 3 3 14 Write Debug Module...

Page 493: ...operation The debug module provides four types of breakpoints PC with mask PC without mask operand address range and data with mask These breakpoints can be configured into one or two level triggers w...

Page 494: ...eaches a sample point which occurs once per instruction Again the hardware forces the PC breakpoint to occur before the targeted instruction executes and is precise This is possible because the PC bre...

Page 495: ...ays puts the processor in emulation mode when debug interrupt exception processing begins Setting CSR TRC forces the processor into emulation mode when trace exception processing begins While operatin...

Page 496: ...wo longwords 27 7 Processor Status Debug Data Definition This section specifies the ColdFire processor and debug module s generation of the processor status PST and debug data DDATA output on an instr...

Page 497: ...DD destination bchg b l Dy ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bclr b l data ea x PST 0x1 PST 0x8 DD source PST 0x8 DD destination bclr b l Dy ea x PST 0x1 PST 0x8 DD source PST 0x8...

Page 498: ...e PST 0x8 DD destination move l ea y ea x PST 0x1 PST 0xB DD source PST 0xB DD destination move w ea y ea x PST 0x1 PST 0x9 DD source PST 0x9 DD destination move w CCR Dx PST 0x1 move w Dy data CCR PS...

Page 499: ...ST 0x1 PST 0xB DD source PST 0xB DD destination suba l ea y Ax PST 0x1 PST 0xB DD source operand subi l data Dx PST 0x1 subq l data ea x PST 0x1 PST 0xB DD source PST 0xB DD destination subx l Dy Dx P...

Page 500: ...or for the taken branch indicator 0x5 2 For JMP and JSR instructions the optional target instruction address is displayed only for those effective address fields defining variant addressing modes This...

Page 501: ...tire time the ColdFire processor is in the given mode 27 8 Freescale Recommended BDM Pinout The ColdFire BDM connector is a 26 pin Berg connector arranged 2 x 13 as shown below msac w Ry Rx PST 0x1 ms...

Page 502: ...mended BDM Connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 Developer reserved1 GND GND RESET EVDD2 GND Freescale reserved GND IVDD BKPT DSCLK Developer reserved1 DSI DSO...

Page 503: ...all data and chip control pins from the board edge connector through the standard four pin test access port TAP and the JTAG reset pin TRST 28 1 1 Block Diagram Figure 28 1 shows the block diagram of...

Page 504: ...mode JTAG_EN 1 Background debug mode BDM for more information refer to Section 27 5 Background Debug Mode BDM JTAG_EN 0 28 2 External Signal Description The JTAG module has five input and one output e...

Page 505: ...information 28 2 3 Test Mode Select Breakpoint TMS BKPT The TMS pin is the test mode select input that sequences the TAP state machine TMS is sampled on the rising edge of TCLK The TMS pin has an inte...

Page 506: ...de 28 3 Memory Map Register Definition The JTAG module registers are not memory mapped and are only accessible through the TDO DSO pin All registers described below are shift in and parallel load 28 3...

Page 507: ...Scan Register The boundary scan register is connected between TDI and TDO when the EXTEST or SAMPLE PRELOAD instruction is selected It captures input pin data forces fixed values on output pins and s...

Page 508: ...g all control signals that execute the JTAG instructions and read write data registers 28 4 2 TAP Controller The TAP controller is a state machine that changes state based on the sequence of logical v...

Page 509: ...ndary scan register while applying fixed values to output pins and asserting functional reset IDCODE 0001 Selects IDCODE register for shift SAMPLE PRELOAD 0010 Selects boundary scan register for shift...

Page 510: ...e sampled data is accessible by shifting it through the boundary scan register to the TDO output by using the shift DR state The data capture and the shift operation are transparent to system operatio...

Page 511: ...t pins during circuit board testing HIGHZ turns off all output drivers including the 2 state drivers and selects the bypass register HIGHZ also asserts internal reset for the MCU system logic to force...

Page 512: ...nized to TCLK internally Any mixed operation using the test logic and system functional logic requires external synchronization Using the EXTEST instruction requires a circuit board test environment t...

Page 513: ...hip modules and Table A 3 is a detailed memory map including all of the registers for on chip modules Table A 1 CPU Space Register Memory Map Address Name Mnemonic Size CPU 0x800 Other Stack Pointer O...

Page 514: ..._0300 I2C0 64 bytes IPSBAR 0x00_0340 QSPI 64 bytes IPSBAR 0x00_0380 I2 C1 64 bytes IPSBAR 0x00_03C0 Real Time Clock 64 bytes IPSBAR 0x00_0400 DMA Timer 0 64 bytes IPSBAR 0x00_0440 DMA Timer 1 64 bytes...

Page 515: ...CWCR 8 IPSBAR 0x0012 Low Power Interrupt Control Register LPICR 8 IPSBAR 0x0013 Core Watchdog Service Register CWSR 8 IPSBAR 0x0014 DMA Request Control Register DMAREQC 32 IPSBAR 0x0018 Peripheral Po...

Page 516: ...nt Register 2 DMA Status Register 2 BCR2 DSR2 32 IPSBAR 0x012C DMA Control Register 2 DCR2 32 IPSBAR 0x0130 Source Address Register 3 SAR3 32 IPSBAR 0x0134 Destination Address Register 3 DAR3 32 IPSBA...

Page 517: ...d UART Receive Buffer 1 URB1 8 UART Write UART Transmit Buffer 1 UTB1 8 IPSBAR 0x0250 Read UART Input Port Change Register 1 UIPCR1 8 Write UART Auxiliary Control Register 11 UACR1 8 IPSBAR 0x0254 Rea...

Page 518: ...UBG22 8 IPSBAR 0x02B4 Read UART Input Port Register 2 UIP2 8 Write Reserved 8 IPSBAR 0x02B8 Read Reserved 8 Write UART Output Port Bit Set Command Register 2 UOP12 8 IPSBAR 0x02BC Read Reserved 8 Wri...

Page 519: ...32 IPSBAR 0x03DC RTC Stopwatch Minutes Register STPWCH 32 IPSBAR 0x03E0 RTC Days Counter Register DAYS 32 IPSBAR 0x03E4 RTC Day Alarm Register ALRM_DAY 32 IPSBAR 0x03F4 RTC General Oscillator Count Up...

Page 520: ...rrupt Pending Register Low 0 IPRL0 32 IPSBAR 0x0C08 Interrupt Mask Register High 0 IMRH0 32 IPSBAR 0x0C0C Interrupt Mask Register Low 0 IMRL0 32 IPSBAR 0x0C10 Interrupt Force Register High 0 INTFRCH0...

Page 521: ...PSBAR 0x0C5A Interrupt Control Register 0 26 ICR026 8 IPSBAR 0x0C5B Interrupt Control Register 0 27 ICR027 8 IPSBAR 0x0C5C Interrupt Control Register 0 28 ICR028 8 IPSBAR 0x0C5D Interrupt Control Regi...

Page 522: ...Register 0 60 ICR060 8 IPSBAR 0x0C7D Interrupt Control Register 0 61 ICR061 8 IPSBAR 0x0C7E Interrupt Control Register 0 62 ICR062 8 IPSBAR 0x0C7F Interrupt Control Register 0 63 ICR063 8 IPSBAR 0x0C...

Page 523: ...ut Data Register PORTAS 8 IPSBAR 0x10_000C Port QS Output Data Register PORTQS 8 IPSBAR 0x10_000D Reserved 8 IPSBAR 0x10_000E Port TA Output Data Register PORTTA 8 IPSBAR 0x10_000F Port TC Output Data...

Page 524: ...DDRTD 8 IPSBAR 0x10_0029 Port UA Data Direction Register DDRUA 8 IPSBAR 0x10_002A Port UB Data Direction Register DDRUB 8 IPSBAR 0x10_002B Port UC Data Direction Register DDRUC 8 IPSBAR 0x10_002C Port...

Page 525: ...0x10_0044 Port DD Pin Data Set Data Register PORTDDP SETDD 8 IPSBAR 0x10_0045 Reserved 8 IPSBAR 0x10_0046 Reserved 8 IPSBAR 0x10_0047 Reserved 8 IPSBAR 0x10_0048 Reserved 8 IPSBAR 0x10_0049 Reserved 8...

Page 526: ...IPSBAR 0x10_0067 Reserved 8 IPSBAR 0x10_0068 Port NQ Pin Assignment Register PNQPAR 16 IPSBAR 0x10_006A Port AN Pin Assignment Register PANPAR 8 IPSBAR 0x10_006B Port AS Pin Assignment Register PASPAR...

Page 527: ...l High Register CCHR 8 IPSBAR 0x12_0009 Clock Control Low Register CCLR 8 IPSBAR 0x12_000A Oscillator Control High Register OCHR 8 IPSBAR 0x12_000B Oscillator Control Low Register OCLR 8 IPSBAR 0x12_0...

Page 528: ...9_000A Sample Disable Register ADSDIS 16 IPSBAR 0x19_000C Status Register ADSTAT 16 IPSBAR 0x19_000E Limit Status Register ADLSTAT 16 IPSBAR 0x19_0010 Zero Crossing Status Register ADZCSTAT 16 IPSBAR...

Page 529: ...Port Data Register GPTPORT 8 IPSBAR 0x1A_001E GPT Port Data Direction Register GPTDDR 8 Pulse Width Modulator IPSBAR 0x1B_0000 PWM Enable Register PWME 8 IPSBAR 0x1B_0001 PWM Polarity Register PWMPOL...

Page 530: ...IPSBAR 0x1B_0020 PWM Channel Duty Register 4 PWMDTY4 8 IPSBAR 0x1B_0021 PWM Channel Duty Register 5 PWMDTY5 8 IPSBAR 0x1B_0022 PWM Channel Duty Register 6 PWMDTY6 8 IPSBAR 0x1B_0023 PWM Channel Duty R...

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