Signal Descriptions
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
2-11
Preliminary
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is three-stateable and
is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
Development Serial Clock. Internally synchronized input. (The logic
level on DSCLK is validated if it has the same value on two
consecutive rising bus clock edges.) Clocks the serial communication
port to the debug module during packet transfers. Maximum frequency
is PSTCLK/5. At the synchronized rising edge of DSCLK, the data
input on DSI is sampled and DSO changes state.
I
Breakpoint
BKPT
Breakpoint. Input used to request a manual breakpoint. Assertion of
BKPT puts the processor into a halted state after the current
instruction completes. Halt status is reflected on processor status
signals as the value 0xF.
I
Development Serial
Input
DSI
Development Serial Input. Internally synchronized input that provides
data input for the serial communication port to the debug module after
the DSCLK has been seen as high (logic 1).
I
Development Serial
Output
DSO
Development Serial Output. Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
O
Debug Data
DDATA[3:0]
Debug data. Displays captured processor data and breakpoint status.
The CLKOUT signal can be used by the development system to know
when to sample DDATA[3:0].
O
Processor Status Clock
PSTCLK
Processor Status Clock. Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and
PST and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be reenabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
O
Processor Status
Outputs
PST[3:0]
Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
O
All Processor Status
Outputs
ALLPST
Logical AND of PST[3.0]
O
Table 2-14. Debug Support Signals (continued)
Signal Name
Abbreviation
Function
I/O
