IEEE 1149.1 Test Access Port (JTAG)
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
28-4
Freescale Semiconductor
Preliminary
28.2.5
Test Reset/Development Serial Clock (TRST/DSCLK)
The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the
TAP controller to the test-logic-reset state.
The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency is 1/5
the processor clock speed. At the rising edge of DSCLK, data input on DSI is sampled and DSO changes
state.
28.2.6
Test Data Output/Development Serial Output (TDO/DSO)
The TDO pin is the lsb-first data output. Data is clocked out of TDO on the falling edge of TCLK. TDO
is tri-stateable and actively driven in the shift-IR and shift-DR controller states.
The DSO pin provides serial output data in BDM mode.
28.3
Memory Map/Register Definition
The JTAG module registers are not memory mapped and are only accessible through the TDO/DSO pin.
All registers described below are shift-in and parallel load.
28.3.1
Instruction Shift Register (IR)
The JTAG module uses a 4-bit shift register with no parity. The IR transfers its value to a parallel hold
register and applies an instruction on the falling edge of TCLK when the TAP state machine is in the
update-IR state. To load an instruction into the shift portion of the IR, place the serial data on the TDI pin
before each rising edge of TCLK. The msb of the IR is the bit closest to the TDI pin, and the lsb is the bit
closest to the TDO pin. See
Section 28.4.3, “JTAG Instructions”
for a list of possible instruction codes.
28.3.2
IDCODE Register
The IDCODE is a read-only register; its value is chip dependent. For more information, see
Section 28.4.3.1, “IDCODE Instruction”
.
TAP state: Update-IR
Access: User read/write
3
2
1
0
R
0
1
0
1
W
Instruction Code
Reset
0
0
0
1
Figure 28-2. 4-Bit Instruction Register (IR)
