ColdFire Core
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
3-20
Freescale Semiconductor
Preliminary
3.3.4.5
Privilege Violation
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. See
ColdFire Programmer’s Reference Manual
for a list of supervisor-mode
instructions.
3.3.4.6
Trace Exception
To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing
capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction
execution (for all but the STOP instruction) signals a trace exception. This functionality allows a debugger
to monitor program execution.
The STOP instruction has the following effects:
1. The instruction before the STOP executes and then generates a trace exception. In the exception
stack frame, the PC points to the STOP opcode.
2. When the trace handler is exited, the STOP instruction executes, loading the SR with the immediate
operand from the instruction.
3. The processor then generates a trace exception. The PC in the exception stack frame points to the
instruction after the STOP, and the SR reflects the value loaded in the previous step.
If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets
SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points
to the instruction after the STOP, and the SR reflects the value loaded in step 2.
Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types. As
an example, consider a TRAP instruction execution while in trace mode. The processor initiates the TRAP
exception and then pass control to the corresponding handler. If the system requires that a trace exception
be processed, it is the responsibility of the TRAP exception handler to check for this condition (SR[T] in
the exception stack frame set) and pass control to the trace handler before returning from the original
exception.
3.3.4.7
Unimplemented Line-A Opcode
A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the
attempted execution of an undefined line-A opcode.
3.3.4.8
Unimplemented Line-F Opcode
A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated when
attempting to execute an undefined line-f opcode.
3.3.4.9
Debug Interrupt
for a detailed explanation of this program module. This exception is
generated in response to a hardware breakpoint register trigger. The processor does not generate an IACK
