Clock Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
6-2
Freescale Semiconductor
Preliminary
next POR. If the relaxation oscillator was already selected as the system clock’s source and is subsequently
selected as the timer’s input source, the system and the timer can use the oscillator as the source.
6.3.2
RTC Mode
A dedicated RTC oscillator can be selected to run the RTC circuitry. In normal operation, this oscillator is
powered by the VDDPLL and VSSPLL pins. When the part is shut down, this oscillator is powered by the
VSTBY pin. The nominal expected frequency for the RTC oscillator is 32.768 kHz, but can range from
32 kHz to 38.4 kHz.
6.3.3
Normal PLL Mode
In normal PLL mode, the PLL is fully programmable. It can synthesize frequencies ranging from 1x to 18x
the reference frequency and has a post divider capable of reducing this synthesized frequency without
disturbing the PLL. The PLL reference can be a crystal oscillator or an external clock.
6.3.4
1:1 PLL Mode
In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external clock input reference frequency.
The post divider is not active.
6.3.5
External Clock Mode
In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL. The resulting
operating frequency is equal to the external clock frequency.
6.4
Low-Power Mode Operation
This subsection describes the operation of the clock module in low-power and halted modes of operation.
Low-power modes are described in
Chapter 8, “Power Management.”
shows the clock module
operation in low-power modes.
Table 6-1. Clock Module Operation in Low-power Modes
In wait and doze modes, the system clocks to the peripherals are enabled and the clocks to the CPU and
SRAM are stopped. Each module can disable its clock locally at the module level.
Low-power Mode
Clock Operation
Mode Exit
Wait
Clocks sent to peripheral modules only
Exit not caused by clock module, but normal
clocking resumes upon mode exit
Doze
Clocks sent to peripheral modules only
Exit not caused by clock module, but normal
clocking resumes upon mode exit
Stop
All system clocks disabled
Exit not caused by clock module, but clock
sources are re-enabled and normal clocking
resumes upon mode exit
Halted
Normal
Exit not caused by clock module
