Clock Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
6-19
Preliminary
Figure 6-12. Crystal Oscillator Example
6.8.4.1
Phase and Frequency Detector (PFD)
The PFD is a dual-latch phase-frequency detector. It compares the phase and frequency of the reference
and feedback clocks. The reference clock comes from the crystal oscillator or an external clock source.
The feedback clock comes from one of the following:
•
CLKOUT in 1:1 PLL mode
•
VCO output divided by two if CLKOUT is disabled in 1:1 PLL mode
•
VCO output divided by the MFD in normal PLL mode
When the frequency of the feedback clock equals the frequency of the reference clock, the PLL is
frequency-locked. If the falling edge of the feedback clock lags the falling edge of the reference clock, the
PFD pulses the UP signal. If the falling edge of the feedback clock leads the falling edge of the reference
clock, the PFD pulses the DOWN signal. The width of these pulses relative to the reference clock depends
on how much the two clocks lead or lag each other. After phase lock is achieved, the PFD continues to
pulse the UP and DOWN signals for very short durations during each reference clock cycle. These short
pulses continually update the PLL and prevent the frequency drift phenomenon known as dead-banding.
6.8.4.2
Charge Pump/Loop Filter
In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode the current magnitude of the
charge pump varies with the MFD as shown in
.
The UP and DOWN signals from the PFD control whether the charge pump applies or removes charge,
respectively, from the loop filter. The filter is integrated on the chip.
Table 6-17. Charge Pump Current and MFD in Normal Mode Operation
Charge Pump Current
MFD
1x
0
≤
MFD < 2
2x
2
≤
MFD < 6
4x
6
≤
MFD
V
SSPLL
V
SSPLL
EXTAL
XTAL
RF
C1
C2
ON-CHIP
8 MHz CRYSTAL CONFIGURATION
C1 = C2 = 16 pF
RF = 1 M
Ω
R1
R1 = 1 M
Ω
