Overview
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
1-9
Preliminary
The full debug/trace interface is available only on the 100-pin packages. However, every product features
the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.3
JTAG
The MCF52110 supports circuit board test strategies based on the Test Technology Committee of IEEE
and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a
16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit
boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into
one shift register. Test logic, implemented using static logic design, is independent of the device system
logic.
The MCF52110 implementation can:
•
Perform boundary-scan operations to test circuit board electrical continuity
•
Sample
MCF52110
system
pins
during
operation and transparently shift out the result
in the
boundary scan register
•
Bypass the MCF52110 for a given circuit board test by effectively reducing the
boundary-scan
register to a single bit
•
Disable the output drive to pins during circuit-board testing
•
Drive output pins to stable levels
1.2.4
On-Chip Memories
1.2.4.1
SRAM
The dual-ported SRAM module provides a general-purpose 16-Kbyte memory block that the ColdFire
core can access in a single cycle. The location of the memory block can be set to any 16-Kbyte boundary
within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for
use as the system stack. Because the SRAM module is physically connected to the processor's high-speed
local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug
module.
The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal
for implementing applications with double-buffer schemes, where the processor and a DMA device
operate in alternate regions of the SRAM to maximize system performance.
1.2.4.2
Flash Memory
The ColdFire flash module (CFM) is a non-volatile memory (NVM) module that connects to the
processor’s high-speed local bus. The CFM is constructed with four banks of 16-Kbyte
×
16-bit flash
memory arrays to generate 128 Kbytes of 32-bit flash memory. These electrically erasable and
programmable arrays serve as non-volatile program and data memory. The flash memory is ideal for
program and data storage for single-chip applications, allowing for field reprogramming without requiring
an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only
memory controller that supports interleaved accesses from the 2-cycle flash memory arrays. A backdoor
