ColdFire Flash Module (CFM)
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
17-17
Preliminary
17.4.2
Flash Normal Mode
In flash normal mode, the user can access the CFM registers and the CFM flash memory (see
).
17.4.2.1
Read Operation
A valid read operation occurs when a transfer request is initiated, the address is equal to an address within
the valid range of the CFM flash memory space, and the read/write control indicates a read cycle.
17.4.2.2
Write Operation
A valid write operation occurs when a transfer request is initiated, the address is equal to an address within
the valid range of the CFM flash memory space and the read/write control indicates a write cycle. The
action taken on a valid flash array write depends on the subsequent user command issued as part of a valid
command write sequence. Only 32-bit write operations are allowed to the flash memory space. Byte and
half-word write operations to the flash memory space results in a cycle termination transfer error.
17.4.2.3
Program, Erase, and Verify Operations
Write and read operations are used for the program, erase, and verify algorithms described in this section.
These algorithms are controlled by the flash memory controller whose timebase, for program and erase
operations, is derived from the internal flash bus clock via a programmable counter. The command register
as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO), so that
a new command along with the necessary data and address can be stored to the buffer while the previous
command is in progress. This buffering operation provides time optimization when programming more
than one word on a physical row in the flash memory as the high voltage generation can be kept active in
between two programming operations. This saves the time overhead needed for setup of the high voltage
charge pumps. Buffer empty, as well as command completion, is signaled by flags in the CFMUSTAT
register with interrupts generated, if enabled.
The next four sections describe:
•
How to write the CFMCLKD register
•
Command write sequences used to program, erase, and verify the flash memory
•
Valid flash commands
•
Errors resulting from illegal command write sequences to the flash memory
17.4.2.3.1
Writing the CFMCLKD Register
Prior to issuing any command, it is necessary to write the CFMCLKD register to divide the input clock to
within the 150 KHz to 200 KHz range. The CFMCLKD register bits, PRDIV8 and DIV, are set as follows:
For frequencies of the input clock greater than 12.8 MHz, the CFMCLKD bit PRDIV8 must be set.
CFMCLKD DIV bit field must be chosen so that the following equation is valid:
If PRDIV8 == 1 then FCLK = input clock / 8, else FCLK = input clock
If (FCLK[KHz] / 200KHz) is integer then DIV = (FCLK[KHz] / 200KHz) - 1,
else DIV = INT (FCLK[KHz] / 200kHz)
