DMA Timers (DTIM0–DTIM3)
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
21-4
Freescale Semiconductor
Preliminary
21.2.2
DMA Timer Extended Mode Registers (DTXMR
n
)
The DTXMR
n
register programs DMA request and increment modes for the timers.
Table 21-2. DTMR
n
Field Descriptions
Field
Description
15–8
PS
Prescaler value. The prescaler is programmed to divide the clock input (internal bus clock/(16 or 1) or clock on
DTIN
n
) by values from 1 (PS equals 0x00) to 256 (PS equals 0xFF).
7–6
CE
Capture edge.
00 Disable capture event output
01 Capture on rising edge only
10 Capture on falling edge only
11 Capture on any edge
5
OM
Output mode.
0 Active-low pulse for one internal bus clock cycle (-ns resolution at MHz).
1 Toggle output.
4
ORRI
Output reference request, interrupt enable. If ORRI is set when DTER
n
[REF] equals 1, a DMA request or an interrupt
occurs, depending on the value of DTXMR
n
[DMAEN] (DMA request if equals 1, interrupt if equals 0).
0 Disable DMA request or interrupt for reference reached (does not affect DMA request or interrupt on capture
function).
1 Enable DMA request or interrupt upon reaching the reference value.
3
FRR
Free run/restart
0 Free run. Timer count continues incrementing after reaching the reference value.
1 Restart. Timer count is reset immediately after reaching the reference value.
2–1
CLK
Input clock source for the timer
00 Stop count
01 Internal bus clock divided by 1
10 Internal bus clock divided by 16. This clock source is not synchronized with the timer; therefore, successive
time-outs may vary slightly.
11 DTIN
n
pin (falling edge)
0
RST
Reset timer. Performs a software timer reset similar to an external reset, although other register values can be written
while RST equals 0. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless
the timer is enabled.
0 Reset timer (software reset)
1 Enable timer
IPSBAR
Offset:
0x00_0402
(
DTXMR0
)
0x00_0442
(
DTXMR1
)
0x00_0482
(
DTXMR2
)
0x00_04C2
(
DTXMR3
)
Access: User read/write
7
6
5
4
3
2
1
0
R
DMAEN
HALTED
0
0
0
0
0
MODE16
W
Reset:
0
0
0
0
0
0
0
0
Figure 21-3. DTXMR
n
Registers
