Queued Serial Peripheral Interface (QSPI)
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
22-13
Preliminary
The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following
expression:
Eqn. 22-1
22.4.3
Transfer Delays
The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer. The time
between QSPI_CS assertion and the leading QSPI_CLK edge, and the time between the end of one transfer
and the beginning of the next, are both independently programmable.
The chip select to clock delay enable bit in command RAM, QCR[DSCK], enables the programmable
delay period from QSPI_CS assertion until the leading edge of QSPI_CLK. QDLYR[QCD] determines the
period of delay before the leading edge of QSPI_CLK. The following expression determines the actual
delay before the QSPI_CLK leading edge:
Eqn. 22-2
QDLYR[QCD] has a range of 1–127.
When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the QSPI_CLK period
is used.
The command RAM delay after transmit enable bit, QCR[DT], enables the programmable delay period
from the negation of the QSPI_CS signals until the start of the next transfer. The delay after transfer can
be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive
transfers to allow serial A/D converters to complete conversion. There are two transfer delay options: the
user can choose to delay a standard period after serial transfer is complete or can specify a delay period.
Writing a value to QDLYR[DTL] specifies a delay period. QCR[DT] determines whether the standard
delay period (DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to
calculate the delay when DT equals 1:
Eqn. 22-3
Table 22-10. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate
Internal Bus Clock = MHz
QMR [BAUD]
QSPI_CLK
2
16.5 MHz
4
8.25 MHz
8
4.1 MHz
16
2.06 MHz
32
1.0 MHz
255
12.9 kHz
QMR[BAUD]
f
sys
2
[desired QSPI_CLK baud rate]
×
-----------------------------------------------------------------------------------
=
QSPI_CS-to-QSPI_CLK delay
QDLYR[QCD]
f
sys
-------------------------------------
=
Delay after transfer
32
QDLYR[DTL]
×
f
sys
------------------------------------------------
(DT = 1)
=
