UART Modules
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
23-8
Freescale Semiconductor
Preliminary
IPSBAR
Offset:
0x00_0204 (USR0)
0x00_0244 (USR1)
0x00_0284 (USR2)
Access: User read-only
7
6
5
4
3
2
1
0
R
RB
FE
PE
OE
TXEMP
TXRDY
FFULL
RXRDY
W
Reset:
0
0
0
0
0
0
0
0
Figure 23-5. UART Status Registers (USR
n
)
Table 23-5. USR
n
Field Descriptions
Field
Description
7
RB
Received break. The received break circuit detects breaks originating in the middle of a received character. However,
a break in the middle of a character must persist until the end of the next detected character time.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. Only a single FIFO position is
occupied when a break is received. Further entries to the FIFO are inhibited until URXD
n
returns to the high state
for at least one-half bit time, which equals two successive edges of the UART
clock. RB is valid only when RXRDY
equals 1.
6
FE
Framing error.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check
occurs in the middle of the first stop-bit position. FE is valid only when RXRDY equals 1.
5
PE
Parity error. Valid only if RXRDY equals 1.
0 No parity error occurred.
1 If UMR1
n
[PM] equals 0
x
(with parity or force parity), the corresponding character in the FIFO was received with
incorrect parity. If UMR1
n
[PM] equals 11 (multidrop), PE stores the received address or data (A/D) bit. PE is valid
only when RXRDY equals 1.
4
OE
Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character
when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this
occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any,
are lost. The
RESET
ERROR
STATUS
command in UCR
n
clears OE.
3
TEMP
Transmitter empty.
0 The transmit buffer is not empty. A character is shifted out, or the transmitter is disabled. The transmitter is
enabled/disabled by programming UCR
n
[TC].
1 The transmitter has underrun (the transmitter holding register and transmitter shift registers are empty). This bit
is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding
register awaiting transmission.
2
TXRDY
Transmitter ready.
0 The CPU loaded the transmitter holding register, or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the
transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded
into the transmitter holding register are not sent.
