UART Modules
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
23-15
Preliminary
23.3.11 UART Baud Rate Generator Registers (UBG1
n
/UBG2
n
)
The UBG1
n
registers hold the MSB, and the UBG2
n
registers hold the LSB of the preload value. UBG1
n
and UBG2
n
concatenate to provide a divider to the internal bus clock for transmitter/receiver operation,
Section 23.4.1.2.1, “Internal Bus Clock Baud Rates
NOTE
The minimum value loaded on the concatenation of UBG1
n
with UBG2
n
is
0x0002. The UBG2
n
reset value of 0x00 is invalid and must be written to
before the UART transmitter or receiver are enabled. UBG1
n
and UBG2
n
are write-only and cannot be read by the CPU.
23.3.12 UART Input Port Register (UIP
n
)
The UIP
n
registers, shown in
, show the current state of the UCTS
n
input.
IPSBAR
Offset:
0x00_0218 (UBG10)
0x00_0258 (UBG11)
0x00_0298 (UBG12)
Access: User write-only
7
6
5
4
3
2
1
0
R
W
Divider MSB
Reset:
0
0
0
0
0
0
0
0
Figure 23-13. UART Baud Rate Generator Registers (UBG1
n
)
IPSBAR
Offset:
0x00_021C (UBG20)
0x00_025C (UBG21)
0x00_029C (UBG22)
Access: User write-only
7
6
5
4
3
2
1
0
R
W
Divider LSB
Reset:
0
0
0
0
0
0
0
0
Figure 23-14. UART Baud Rate Generator Registers (UBG2
n
)
IPSBAR
Offset:
0x00_0234 (UIP0)
0x00_0274 (UIP1)
0x00_02B4 (UIP2)
Access: User read-only
7
6
5
4
3
2
1
0
R
1
1
1
1
1
1
1
CTS
W
Reset:
1
1
1
1
1
1
1
1
Figure 23-15. UART Input Port Registers (UIP
n
)
