UART Modules
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
23-18
Freescale Semiconductor
Preliminary
Using a 66-MHz internal bus clock and letting baud rate equal 9600, then
Eqn. 23-2
Therefore, UBG1
n
equals 0x00 and UBG2
n
equals 0xD6.
23.4.1.2.2
External Clock
An external source clock (DTIN
n
) passes through a divide-by-1 or 16 prescaler. If f
extc
is the external clock
frequency, baud rate can be described with this equation:
Eqn. 23-3
23.4.2
Transmitter and Receiver Operating Modes
is a functional block diagram of the transmitter and receiver showing the command and
operating registers, which are described generally in the following sections. For detailed descriptions, refer
to
Section 23.3, “Memory Map/Register Definition
.”
Figure 23-18. Transmitter and Receiver Functional Diagram
23.4.2.1
Transmitter
The transmitter is enabled through the UART command register (UCR
n
). When it is ready to accept a
character, UART sets USR
n
[TXRDY]. The transmitter converts parallel data from the CPU to a serial bit
stream on UTXD
n
. It automatically sends a start bit followed by the programmed number of data bits, an
Divider
66
MHz
32 x 9600
[
]
-------------------------------
215
decimal
(
)
0x00D6
hexadecimal
(
)
=
=
=
Baudrate
f
extc
(16 or 1)
---------------------
=
Receiver Shift Register
UART Command Register (UCR
n
)
W
UART Status Register (USR
n
)
R
Transmitter Shift Register
UART Mode Register 1 (UMR1
n
)
R/W
UART Mode Register 2 (UMR2
n
)
R/W
Transmitter Holding Register
W
Receiver Holding Register 3
Receiver Holding Register 2
Receiver Holding Register 1
R
UART Receive
UART
Buffer (URB
n
)
(4 Registers)
UART
n
External
Interface
Transmit Buffer
(UTB
n
)
(2 Registers)
FIFO
URXD
n
UTXD
n
