UART Modules
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
23-21
Preliminary
framing error, overrun error, and received break conditions set the respective PE, FE, OE, and RB error
and break flags in the USR
n
at the received character boundary. They are valid only if USR
n
[RXRDY] is
set.
If a break condition is detected (URXD
n
is low for the entire character including the stop bit), a character
of all 0s loads into the receiver holding register and USR
n
[RB,RXRDY] are set. URXD
n
must return to a
high condition for at least one-half bit time before a search for the next start bit begins.
The receiver detects the beginning of a break in the middle of a character if the break persists through the
next character time. If the break begins in the middle of a character, receiver places the damaged character
in the Rx FIFO and sets the corresponding USR
n
error bits and USR
n
[RXRDY]. Then, if the break lasts
until the next character time, receiver places an all-zero character into the Rx FIFO and sets
USR
n
[RB,RXRDY].
shows receiver functional timing.
Figure 23-20. Receiver Timing Diagram
23.4.2.3
FIFO
The FIFO is used in the UART’s receive buffer logic. The FIFO consists of three receiver holding registers.
The receive buffer consists of the FIFO and a receiver shift register connected to the URXD
n
(see
). Data is assembled in the receiver shift register and loaded into the top empty receiver
holding register position of the FIFO. Therefore, data flowing from the receiver to the CPU is
quadruple-buffered.
In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break
(RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By
C1
C2
C4
C6
C7
C8
C3
C5
C6, C7, and C8 will be lost
(C2)
Status
Data
(C3)
Status
Data
(C4)
Status
Data
C5 will
be lost
Reset by
command
Receiver
Enabled
USR
n
[RXRDY]
Overrun
internal
module
select
USR
n
[FFULL]
(C1)
Status
Data
USR
n
[OE]
Automatically asserted
when ready to receive
Manually asserted first time,
automatically negated if overrun occurs
UOP0[RTS] = 1
1
UMR2
n
[RXRTS] = 1
URXD
n
URTS
1
