I
2
C Interface
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
24-3
Preliminary
The interface operates up to 100 Kbps with maximum bus loading and timing. The device is capable of
operating at higher baud rates, up to a maximum of the internal bus clock divided by 20, with reduced bus
loading. The maximum communication length and the number of devices connected are limited by a
maximum bus capacitance of 400 pF.
The I
2
C system is a true multiple-master bus; it uses arbitration and collision detection to prevent data
corruption in the event that multiple devices attempt to control the bus simultaneously. This feature
supports complex applications with multiprocessor control and can be used for rapid testing and alignment
of end products through external connections to an assembly-line computer.
NOTE
The I
2
C module is compatible with the Philips I
2
C bus protocol. For
information on system configuration, protocol, and restrictions, see
The I
2
C
Bus Specification, Version 2.1
.
NOTE
The GPIO module must be configured to enable the peripheral function of
the appropriate pins (refer to
Chapter 13, “General Purpose I/O Module”
)
prior to configuring the I
2
C module.
24.1.3
Features
The I
2
C module has these key features:
•
Compatibility with I
2
C bus standard version 2.1
•
Support for 3.3-V tolerant devices
•
Multiple-master operation
•
Software-programmable for one of 50 different serial clock frequencies
•
Software-selectable acknowledge bit
•
Interrupt-driven, byte-by-byte data transfer
•
Arbitration-lost interrupt with automatic mode switching from master to slave
•
Calling address identification interrupt
•
START and STOP signal generation/detection
•
Repeated START signal generation
•
Acknowledge bit generation/detection
•
Bus-busy detection
24.2
Memory Map/Register Definition
The below table lists the configuration registers used in the I
2
C interfaces.
