I
2
C Interface
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
24-12
Freescale Semiconductor
Preliminary
24.3.7
Clock Synchronization and Arbitration
I
2
C is a true multi-master bus that allows more than one master connected to it. If two or more master
devices simultaneously request control of the bus, a clock synchronization procedure determines the bus
clock. Because wire-AND logic is performed on the SCL line, a high-to-low transition on the SCL line
affects all the devices connected on the bus. The devices start counting their low period and after a device’s
clock has gone low, it holds the SCL line low until the clock high state is reached. However, change of low
to high in this device’s clock may not change the state of the SCL line if another device clock remains
within its low period. Therefore, synchronized clock SCL is held low by the device with the longest low
period.
Devices with shorter low periods enter a high wait state during this time (see
). When all
devices concerned have counted off their low period, the synchronized clock (SCL) line is released and
pulled high. At this point, the device clocks and the SCL line are synchronized, and the devices start
counting their high periods. The first device to complete its high period pulls the SCL line low again.
Figure 24-12. Clock Synchronization
A data arbitration procedure determines the relative priority of the contending masters. A bus master loses
arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters immediately
switch over to slave receive mode and stop driving SDA output (see
). In this case, transition
from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets I2SR[IAL] to
indicate loss of arbitration.
Figure 24-13. Arbitration Procedure
Internal Counter Reset
Wait
Start counting high period
SCL1
SCL2
SCL
Master 2 Loses Arbitration,
and becomes slave-receiver
SCL
SDA by
Master1
SDA by
Master2
SDA
