Analog-to-Digital Converter (ADC)
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
25-15
Preliminary
Negative results (SEXT = 1) are always presented in twos-complement format. If an application requires
that the result be always positive, the corresponding offset register (ADOFS
n)
must be set to 0x0.
The interpretation of the numbers programmed into the ADC limit and offset registers (ADLLMT
n
,
ADHLMT
n
, and ADOFS
n
) must match your interpretation of the result register.
25.4.10 Low and High Limit Registers (ADLLMT
n
and ADHLMT
n
)
Each ADC sample is compared against the values in the limit registers. The comparison is based upon the
raw conversion value before the offset correction is applied. Refer to
ADC limit registers
(ADLLMT
n
and ADHLMT
n)
correspond to result registers (ADRSLT
n
). The high limit register is used
for the comparison of result > high limit. The low limit register is used for the comparison of result < low
limit.
Limit checking can be disabled by programming the respective limit register with 0x7FF8 for the high
limit and 0x0000 for the low limit. At reset, limit checking is disabled.
IPSBAR
Offsets:
0x19_0012 (ADRSLT0)
0x19_0014 (ADRSLT1)
0x19_0016 (ADRSLT2)
0x19_0018 (ADRSLT3)
0x19_001A (ADRSLT4)
0x19_001C (ADRSLT5)
0x19_001E (ADRSLT6)
0x19_0020 (ADRSLT7)
Access: read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R SEXT
RSLT
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-12. Result Registers (ADRSLT
n
)
Table 25-14. ADRSLT
n
Field Descriptions
Field
Description
15
SEXT
Sign Extend bit.
0 Result is positive
1 Result is negative
Note:
If only positive results are required, then the respective offset register (ADOFS
n
) must be set to 0x0.
14–3
RSLT
Result of the conversion.
2–0
Reserved, should be cleared.
