Analog-to-Digital Converter (ADC)
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
25-27
Preliminary
Figure 25-22. Typical Connections for Differential Measurements
25.5.3
ADC Data Processing
, the raw result of the ADC conversion process is sent to an adder for offset
correction. The adder subtracts the ADOFS
n
register value from each sample and the result is stored in the
corresponding result register (ADRSLT
n
). Concurrent to this the raw ADC value is checked for limit
violations, and the ADRSLT
n
values are checked for zero-crossing. Appropriate interrupts are asserted, if
enabled.
The sign of the result is calculated from the ADC unsigned result minus the respective offset register. If
the offset register is programmed with a value of zero, the result register value is unsigned and equals the
cyclic converter unsigned result. The range of the result registers (ADRSLT
n
) is 0x0000–0x7FF8,
assuming the offset (ADOFS
n
) registers are set to zero.
The processor can write to the result registers when the ADC is in stop mode or powered down. The data
from this write operation is treated as if it came from the ADC analog core; so the limit checking, zero
crossing, and the offset registers function as if in normal mode. For example, if the ADC is stopped and
the processor writes to ADRSLT5, the data written to ADRSLT5 is muxed to the ADC digital logic inputs,
processed, and stored into ADRSLT5, as if the analog core had provided the data. This test data must be
left justified by 3 bits (as shown in the ADRSLT register definition) and does not include the sign bit. The
sign bit (SEXT) is calculated during subtraction of the corresponding ADOFS
n
offset value.
+
–
AN+
AN–
Differential buffer centers about mid-point
AN+
AN–
V
REF
/2
Center tap held at (V
REFH
+ V
REFL
) /2
NOTE: Normally, V
REFL
is
V
REFH
Potential
set to V
SSA
= 0V
