Analog-to-Digital Converter (ADC)
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
25-32
Freescale Semiconductor
Preliminary
25.5.7
Interrupt Sources
illustrates how five interrupt sources are combined into three entries in the interrupt vector
table.
Figure 25-24. ADC Interrupt Sources
25.5.8
Power Management
The five supported power modes are described below. They are in order of highest to lowest power
utilization at the expense of increased conversion latency and/or startup delay. Please see
,” for details of the various clocks referenced below.
25.5.8.1
Power Management Modes
1. Normal power mode
This mode operates when:
— At least one ADC converter is powered up (PD0 or PD1=0 in the POWER register);
— Auto power-down and auto standby modes are disabled (APD=0, ASB=0 in the POWER
register);
— The ADC’s clock is enabled (ADC=1 in the SIM module’s SIM_PCE register).
In this mode, the ADC uses the conversion clock as the ADC clock source when active or idle. To
minimize conversion latency, it is recommended the conversion clock be configured to 5.0 MHz. No
startup delay (defined by PUDELAY in the POWER register) is imposed.
2. Auto power-down mode
This mode operates when:
— At least one ADC converter is powered up (PD0 or PD1=0 in the POWER register);
— Auto power-down mode is enabled (APD=1 in the POWER register);
— The ADC’s clock is enabled (ADC=1 in the SIM module’s SIM_PCE register).
Auto power-down and standby modes can be used together by setting APD equal to 1 in the above
configuration. This hybrid mode converts at an ADC clock rate of 100 kHz using standby current mode
when active, and gates off the ADC clock and powers down the converters when idle. A startup delay of
EOSI0
EOSIE0
EOSI1
EOSIE1
ZCI
ZCIE
ADC Zero Crossing or Limit Error
LLMTIE
HLMTI
HLTMIE
LLMTI
(ADC_ERR_INT)
ADCB Conversion Complete
(ADC_CC1_INT)
ADCA Conversion Complete
(ADC_CC0_INT)
