Pulse-Width Modulation (PWM) Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
26-5
Preliminary
26.2.4
PWM Prescale Clock Select Register (PWMPRCLK)
The PWMPRCLK register selects the prescale clock source for clocks A and B independently. If the clock
prescale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during
the transition.
IPSBAR
Offset:
0x1B_0002 (PWMCLK)
Access: User Read/Write
7
6
5
4
3
2
1
0
R
PCLK7
PCLK6
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
W
Reset:
0
0
0
0
0
0
0
0
Figure 26-4. PWM Clock Select Register (PWMCLK)
Table 26-4. PWMCLK Field Descriptions
Field
Description
7–0
PCLK
n
PWM channel
n
clock select. Selects between one of two clock sources for each PWM channel. See
“PWM Prescale Clock Select Register (PWMPRCLK)”
and
Section 26.2.7, “PWM Scale A Register (PWMSCLA)”
for
more information on how the different clock rates are generated. The even-numbered channels’ clock select has no
effect when the corresponding PWMCTL[CON
n(n+1)
] bit is set. For example, if PWMCTL[CON01] equals 1,
PWMCLK[PCLK0] has no affect.
IPSBAR
Offset:
0x1B_0003 (PWMPRCLK)
Access: User Read/Write
7
6
5
4
3
2
1
0
R
0
PCKB
0
PCKA
W
Reset:
0
0
0
0
0
0
0
0
Figure 26-5. PWM Prescale Clock Select Register (PWMPRCLK)
PCLK6 & PCLK7
(PWM6 & PWM7
Clock Source)
PCLK4 & PCLK5
(PWM4 & PWM5
Clock Source)
PCLK2 & PCLK3
(PWM2 & PWM3
Clock Source)
PCLK0 & PCLK1
(PWM0 & PWM1
Clock Source)
0
B
A
B
A
1
SB
SA
SB
SA
