Debug Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
27-4
Freescale Semiconductor
Preliminary
Execution speed is affected only when both storage elements contain valid data
to be dumped to the
DDATA port. The core stalls until one FIFO entry is available.
shows the encoding of these signals.
Table 27-3. Processor Status Encoding
PST[3:0]
Definition
0x0
Continue execution. Many instructions execute in one processor cycle. If an instruction requires more clock
cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.
0x1
Begin execution of one instruction. For most instructions, this encoding signals the first processor clock cycle
of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions,
generate different encodings.
0x2
Reserved
0x3
Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to enter
user mode.
0x4
Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug
and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to
the DDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is
signaled on the PST port, followed by the appropriate marker, and then the data transfer on the DDATA port.
Transfer length depends on the WDDATA operand size.
0x5
Begin execution of taken branch or SYNC_PC command issued. For some opcodes, a branch target
address may be displayed on DDATA depending on the CSR settings. CSR also controls the number of
address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins the
data output. See
Section 27.3.1, “Begin Execution of Taken Branch (PST = 0x5)”
. Also indicates that the
SYNC_PC command has been issued.
0x6
Reserved
0x7
Begin execution of return from exception (RTE) instruction.
0x8–
0xB
Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles. The value is
driven onto the PST port one PSTCLK cycle before the data is displayed on DDATA.
0x8 Begin 1-byte transfer on DDATA.
0x9 Begin 2-byte transfer on DDATA.
0xA Begin 3-byte transfer on DDATA.
0xB Begin 4-byte transfer on DDATA.
0xC
Normal exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace)
generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle
mode, PST outputs are driven with 0xC until exception processing completes.
0xD
Emulator mode exception processing.
Displayed during emulation mode (debug interrupt or optionally
trace). Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until
exception processing completes.
0xE
Processor is stopped. Appears in multiple-cycle format when the processor executes a STOP instruction.
The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the
stopped mode is exited.
0xF
Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF until
the processor is restarted or reset. See
