ColdFire Core
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
3-4
Freescale Semiconductor
Preliminary
3.2.1
Data Registers (D0–D7)
D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they
can also be used as index registers.
NOTE
Registers D0 and D1 contain hardware configuration details after reset. See
Section 3.3.4.14, “Reset Exception”
for more details.
3.2.2
Address Registers (A0–A6)
These registers can be used as software stack pointers, index registers, or base address registers; they can
also be used for word and longword operations.
Figure 3-3. Address Registers (A0–A6)
3.2.3
Supervisor/User Stack Pointers (A7 and OTHER_A7)
This ColdFire architecture supports two independent stack pointer (A7) registers—the supervisor stack
pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two
programmable-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead,
0xC05
RAM Base Address Register (RAMBAR)
32
R/W
See Section
Yes
1
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see
.
BDM: Load: 0x080 +
n; n
= 0-7 (D
n
)
Store: 0x180 +
n; n
= 0-7 (D
n
)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
Data
W
Reset
(D2-D7)
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Reset
(D0, D1)
Section 3.3.4.14, “Reset Exception”
Figure 3-2. Data Registers (D0–D7)
BDM: Load: 0x088 +
n; n
= 0–6 (A
n
)
Store: 0x188 +
n; n
= 0–6 (A
n
)
Access: User read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
Address
W
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Table 3-1. ColdFire Core Programming Model (continued)
BDM
1
Register
Width
(bits)
Access
Reset Value
Written with
MOVEC
Section/Page
